Design and implementation of silicon and software for baseband processors conforming to IEEE wireless standards. Initial focus on WiMAX and WiFi.
The main target of this project is to create a Open Source System on Chip generator for FPGA. This generator will use following technologies: Python, Wishbone SoC bus specifications and VHDL.
A methodology to create netlists for printed circuit board layout using a novel PCB specific HDL as the source language.
Powerful Verilog Preprocessor. PLP stands for Perl Pre-processor. Perl is used as "control language" that is embedded in the Verilog code (or any other code) to generate code on the fly. It is used commonly as a Verilog pre-processor but can be used with any target/output language (C, C++, Java, VHDL, plain text etc)
Ray Tracing micro-processor RTMP. Features: * Programmable pixel shaders. * SIMD 32-bit ALU. * Hardware support for Octree scene traversal. * Ray intersection cache. * Support for mutiple instances of RTMP working concurrently.
Verilog Finite State Machine (FSM) Code Generator
SmGen is a finite state machine (FSM) generator for Verilog. On the other hand, it is not an FSM entry tool. The input is behavioral Verilog with clock boundaries specifically set by the designer. SmGen unrolls this behavioral code and generates an FSM from it in synthesizable Verilog. Clock boundaries are explicitly provided by the designer so there is good control on the expected timing
HW(VHDL) and SW of logic analyzer and On-Chip-Verification(OCV) for Value Change Dump(VCD) file format that exported to seemd SystemC ,ModelSIM, and many other EDA tools. Very easy and Simple.
Make your own virtual FPGA system and profile deeply with CI.
TestDrive Profiling Master is a free simulation software for Verilog/SystemVerilog and C/C++. It supports a CI (Continuous Integration) activity for H/W & S/W engineers' cooperation. Run by MS Windows environment, its use is governed by MIT License(Profiles) and LGPLv3(TestDrive Profiling Master). Based on the powerful compiler Verilator and GCC, TestDrive Profiling Master provides a totally free virtual FPGA system environment with various dynamic documents for profiling in deep on your system design. It performs a seamless conversion to a real FPGA environment without any changes of your testing software. I hope you will accomplish a successful design with TestDrive Profiling Master. Q&A : firstname.lastname@example.org
The VHDL Lookup Table Generator generates a table in vhdl from a C++-table. I was too lazy to write a parser. Code is found in the CVS (scroll down for url): http://vhdl-lut-gen.cvs.sourceforge.net/*checkout*/vhdl-lut-gen/vhdl-lut-gen/vhdl-lut-gen.cpp
VSYML is an automated symbolic simulator for VHDL designs.
Tool-independent Makefile generator for VHDL models.
vcomp is a verilog compiler for x86 linux targets - it was a commercial product which is now in the process of being GPL'd
The Verilog-Perl distribution provides Perl preprocessing, parsing and utilities for the Verilog Language. It is also available from CPAN under the Verilog:: namespace.
Tools and libraries for use with systemc and verilog
Tool suite and libraries for developing system-c models. Tools for managing RTL projects.
This library supports interoperability between components written for different verification methodologies such as VMM and OVM. This is maintained by the Accellera Verification Intellectual Property Technical Subcommittee.
Digital waveform viewer/editor. eWave is a visual waveform timing editor compatible with VCD format (with image export possibilities) intended to be used in educational or technological (digital design) purposes. It is distributed as an Eclipse plugin.
Provides a simple way to interact with icarus verilog tool.
The ixo.de USB JTAG pod and firmware allows to access JTAG-capable chips via USB and a protocol like Altera USB-Blaster.
An Open-Source Library for Low-Power Approximate Computing Modules
The “lpACLib” library contains the VHDL description of accurate and approximate versions of several arithmetic modules (like adders and multiplier of different bit-widths) and accelerators. Moreover, it also provides the corresponding software behavioral models/implementations developed in C and MATLAB to enable quality characterization. Besides our novel designs, it also contains implementations for several state-of-the-art arithmetic modules and their approximate versions. This open-source library facilitates research and development in approximate computing at higher abstraction levels, and to facilitate reproducible research and comparisons. In case of usage, please refer to our publication: Muhammad Shafique, Rehan Hafiz, Semeen Rehman, Walaa El-Harouni, Jörg Henkel, "Cross-Layer Approximate Computing: From Logic to Architectures", Design Automation Conference (DAC), 2016. Contributors: Authors, Vanshika Baoni, M. Abdullah Hanif http://ces.itec.kit.edu/lpACLib.php
System on Chip design generator.
SHELLEY Software HardwarE Light LanguagE Yep !
Vaster is a EDA tool. It creates SystemC Cycle Accurate model from VerilogHDL RTL Model.
vcd2svg can parse Value Change Dump (VCD) files and draw an impulse diagram using Scalable Vector Graphics (SVG). It works together with the GHDL open-source simulator.
zuphinx (say zoo'finks) is an efficient VHDL design environment.