Netlist database and manipulation API with interfaces to Java and Ruby. Verilog netlist inputs are supported. Project branch continues to evolve: https://github.com/gburdell/nldb including addition of tclsh UI.
ChronoSVG generates a timing diagram, as used in electrical devices documentations, from a simple and intuitive ASCII source file. The output file is in SVG format, and makes use of CSS to defer the styling details to presentation time.
An EEChip is a chip whose software can evolve. It works like Conway\'s Game of Life, but with highly generic rules for each cell. This project simulates an EEChip in C, and the chips are tested, selected, and mutated in Ruby.
This set will able to generate eeschema libraries, parse KiCAD files (eeschema, eeschema library, netlist), generate Russian GOST specifications for schemes and do other actions.
A wrapper tool for Cotson simulator
A wrapper for Cotson simulator, to automate the installation and simulations of multicore-multinode CPU model
QMod is a semi-analytic model of Out of Order processor performance. The project downloads include MathCAD worksheets, a cycle-based simulator in Java, and helper scripts. See home page for papers.
The goal of this project is to provide an add-on to KLayout (www.klayout.de) to create and visualize a realistic cross-section view for VLSI designs supporting a wide range of technology options.
COTSon scalable simulation infrastructure
With eparts, you can manage your stock of electronic components. You can create and manage projects, part lists, suppliers, buying lists etc. and import projects from EDA tool 'kicad'. It's written with Ruby on Rails.
fhlow is a design environment that handles the design-flow of the digital hardware design process for VHDL desings on FPGAs. It supports Mentor Graphics Modelsim and Altera Quartus by now.