As today’s workforce becomes increasingly connected and mobile at the same time, communicating simply via email or a phone call doesn’t always cut it. Therefore, it is now crucial for businesses to equip their employees with a solution that seamlessly integrates a broad range of communication methods to allow businesses to communicate and collaborate more efficiently. And a Unified Communications (UC) solution is the answer.Sponsored Listing
OSI-Approved Open Source (41)
- GNU General Public License version 2.0 (27)
- GNU Library or Lesser General Public License version 2.0 (8)
- Artistic License (3)
- BSD License (2)
- GNU General Public License version 3.0 (2)
- GNU Library or Lesser General Public License version 3.0 (2)
- MIT License (2)
- Mozilla Public License 1.0 (2)
- Apache License V2.0 (1)
- MITRE Collaborative Virtual Workspace License (1)
- Mozilla Public License 1.1 (1)
- Sun Public License (1)
- Public Domain (2)
- Other License (1)
- Linux (41)
- Grouping and Descriptive Categories (33)
- Windows (26)
- BSD (23)
- Modern (20)
- Mac (15)
- Solaris (7)
- Android (5)
- Emulation and API Compatibility (4)
- Programming Language: Perl ×
The Verilog-Perl distribution provides Perl preprocessing, parsing and utilities for the Verilog Language. It is also available from CPAN under the Verilog:: namespace.
Provides a GPL'd test suite for verification of the verilog language. This project is affiliated with the Icarus Verilog compiler effort at icarus.com, and test reports are collected from that project.
Testing for modern techniques, algorithms and optimization methods.
You’re probably paying too much for cell phone service. Wirefly compares hundreds of plans to help you save. Enter what you need (minutes, data, texts) into Wirefly’s innovative plan comparison tools and see your savings instantly.Sponsored Listing
Magnetostatic finite differences simulation tool based on GNU Octave and a Perl/Tk user interface.
Bobware tool suite is a set of small EDA tools which are useful in the design of integrated circuits. The suite contains a perl/tk script for region planning large ASICs (application specific integrated circuits.)1 weekly downloads
unPIC is a Perl script that disassembles Microchip microcontroller's HEX files. This is a powerful tool for all reverse engeneers that creates a well understandable assembly source from a binary file. Creates xrefs, labels, subroutines and much more...1 weekly downloads
Verilator converts synthesizable Verilog HDL modules into SystemC modules. This enables users with Verilog code to have a publicly available co-simulation environment. For all information, see http://www.veripool.com/verilator.html.
Grid-tools is a collection of scripts to aid in the submission of complex jobs to either Sun Grid Engine or LSF.
GBTiler, a Gerber circuit board tiling program allows engineers, electronics hobbyists and other users with Gerber RS274X format files to "tile" or combine separate Gerber files -- circuit boards -- into a single, valid Gerber formatted file.18 weekly downloads
Capsim(r) C Text Mode Kernel(TMK),DSP and communication blocks, topologies, libraries and tools for the development of high performance block diagram digital signal processing and communications systems,built in interpreter for scripting.SystemC support.
toolbox with information and programs for Computer Aided Innovation The scientific background of Skidbladnir is known as the Theory of Inventive Problem Solving; in English abbreviated as TIPS or TRIZ, in German as TRIS.
Project to develop an open toolkit (primarily) for the design of power kites.
ChipVault is a project organizer for VHDL and Verilog RTL hardware designs. It provides rapid hierarchy navigation and includes Revision Control and hooks to launching external tools. ChipVault is written in Perl and is small, fast and efficient.
a set of free tools and software aimed at design automation. SPICE ( NG-spice )MAGIC XCIRCUIT Main aim - to automate the layout of clock distribution on a chip, using rotary clock oscilation.
Source Navigator for Verilog is a verilog parser that allows Source Navigator to be used with the Verilog Hardware Description Language. http://sources.redhat.com/sourcenav1 weekly downloads
Libraries for building tools and scripts for ECAD. Contains physical, circuit and Verilog libraries bolted into the 'carrion' module.
zuphinx (say zoo'finks) is an efficient VHDL design environment.