The idea of this project is automatize hydrogen Booster system created by Stanley Meyer to implement it in cars,trucks and electric plants as well as for production of free energy.
Register Interface Description tool
A tool to descibe sets of memory mapped registers and to generate different outputs, e.g. C header files, Verilog source code, HTML documets, from that description. This tool is written in Java and uses ANTLR for parsing and StringTemplates for output generation.
Java Decision Diagrams (BDD) libraries: JDD and JBDD
This project used to contain two decision diagrams libraries: - JBDD: a Java interface to two popular BDD libraries, CUDD and BuDDy - JDD: a native Java library supporting BDD, Z-BDD Both projects have now been moved to bitbucket.org: - https://bitbucket.org/vahidi/jbdd/wiki/Home - https://bitbucket.org/vahidi/jdd/wiki/Home If you are wondering why the move was made after 14 years (!!) on SourceForge, I suggest you read this article: http://arstechnica.com/information-technology/2015/05/sourceforge-grabs-gimp-for-windows-account-wraps-installer-in-bundle-pushing-adware/
O Projeto Cleusa - É uma interface de Gerenciamento de dispositivos. O projeto ROSANA aciona ações nos relês. O projeto Cleusa utiliza uma dispositivo de Hardware especifico, porem pode ser compatibilizado com qualquer outro hardware.
IVI is a graphical, interactive user-interface to various Open-Source HDL simulators. IVI is transitioning to using the Eclipse application framework.
A collection of HDL (Verilog, VHDL) tools
I'll write this later
Open source JTAG/Boundary Scan platform
JSDAI is a toolkit for STEP (ISO 10303), the STandard for the Exchange of Product Model data, that enables linking of CAD, CAM, PDM, PLM, CAx systems. JSDAI supports the development of Express data models (ISO 10303-11) and their implementation in Java.
A Java API for manipulation of GDSII stream data. It is intended to provide a useful, reusable and platform independant library for CAD/CAE application developers. This API Requires the Java Backus-Naur Test API (JBNT). You may download it from: ht
Application able to simplify and make calculations involving a circuit built by the user.
SHELLEY Software HardwarE Light LanguagE Yep !
PIC Development Studio is a simulator for the PIC16F84 microcontroller. It also provides a plugin framework making it possible to develop custom components. A library of ready-made components is included.
PCB-Tools is a system independent, a Java programmed Eclipse-RCP application for developing circuit diagrams and printed circuit boards. It uses Eclipse Graphical Editor Framework (GEF) to draw diagrams and layouts.
Java source to C source translator, which allows to write MCU programs in Java. Now AVR are supported, others can be added. Convenient Java methods instead of manual register handling.
The aim of this project is to implement a channel router using the left-edge algorithm.
The aim of this project is to develop a GDSII viewer by using Java programming language. Efforts will be made especially on ease-of-use, efficiency, and capacity.
Digital waveform viewer/editor. eWave is a visual waveform timing editor compatible with VCD format (with image export possibilities) intended to be used in educational or technological (digital design) purposes. It is distributed as an Eclipse plugin.
Netlist database and manipulation API with interfaces to Java and Ruby. Verilog netlist inputs are supported. Project branch continues to evolve: https://github.com/gburdell/nldb including addition of tclsh UI.
Modelio-Open is a project hosting a set of open source extensions (SoaML, SysML and UML Testing Profile) for a previous version (1.2) of the Modelio Free tool . Currently, the lastest version (2.x) of Modelio modeling and generation tool is available at http://modelio.org/downloads/download-modelio.html. All extensions are downloadable at http://forge.modelio.org/projects.
A suite of calculators and conversion tools for engineers.
Includes a signal scaling app, many engineering unit conversion calcs, and a task list pad to keep track of progress or notes.
The Boolean Expression Reducer provides the user with various tools to visualize and analyze boolean expressions. Given an expression, it also reduces it to its Sum of Products and Product of Sums form.
Nocmaker is a tool for the design space exploration tool to help in the design of Network on chips. Noc Maker is based on JHDL.
PPPP is a computer program used for partitioning parameterized orthogonal polygons into parameterized rectangles. With this program, it is possible to build rectangular corner stitching data structure for parameterized VLSI layouts.
Currently, all existing formal tools are designed to serve as formal verifiers, using one implementation or another. JTLV is a new tool aimed to facilitate and provide a unified framework to the development of formal verification algorithms.
This is an applet used id Warsaw University of Technology for education. It simulates a double port element by the "s" matrix. The applet implements an MVC model.