Caneda (Circuits and Networks EDA) is an open source EDA software.
Caneda (Circuits and Networks EDA) is an open source EDA software focused on easy of use and portability. While in the short term schematic capture and simulation is the primary goal, in the long term future, PCB and layout edition will be covered.
CoreTML framework is an open-source template-based configuration system allowing the developer to create parametrized templates by inserting special content to any text files. Its main purpose is to serve as a toolkit for semiconductor IP core creation (based on VHDL/Verilog).
Microdev is a complete development tool dedicated to microcontroller based boards. It is composed of a graphical and real time simulator and a full featured editor supporting Picbasic, JAL and Asm.
Current work at: https://github.com/jcampos73/DraftCable WARNING: version 1.0.94 previous to 2016-01-22 has a BUG! Download again! Min. Req: Win XP SP3 If you get missing mfc120.dll install vcredist_x86.exe at prog folder CAD design tool for electrical and block diagrams with net list compilation. Tool for creating new parts included. DO NOT lose time copy and pasting cable datasheet. This program, unlike MS Visio or other generic tools, has specific business funcionalities like: 1.- You can double-click a cable in the diagram and define the wiring of that cable in a pop-up dialog. 2.- Also the parts have properties that define all the connector Jacks / Plugs (J/P) they have (e.g., J1 or P1 would appear at the part). 3.- Rack lay out tool. You can associate each part with its rack view equivalent. For example: you can associate a part that is a Server with a rack part of 4U height to place at the rack This software produces block diagrams and wiring sheets
dark themed version of free Audacity sound editor
audacity-extra now provides a sleek dark themed version of the Audacity open source sound editor. The project experiments with Audacity variations. There's a vowel-sound target-practice display for language learners and an analog waveform data logger for embedded systems.
Capind is a program for calculating RLGC matrix of multi-conductor transmission lines of arbitrary shape and dielectric configuration. Capind is based on finite difference method and features easy-to-use input files and optional graphical interface.
SCLive is a modular Linux-Live Distribution dedicated to the OSCI SystemC simulator and it's associated libraries. The distribution provides a fully working environement including a simulator kernel, wavefom viewer, IDE, tutorials and more.
A parser to check the syntax of Touchstone 2.0 data files.
VMW is a software for students of Engineering/Science/Mathematics that can be used for solving mathematical problems in their field.
Lossi (LOgikSchaltungsSImulator - german for "logic circuit simulator"). It simulates logic circuits. Really.
Template based CPP arithmetic class for fixed precision arithmetic.
Verilog test frame generator - used for performance testing of Verilog run time systems.
A Hardware/Software Co-Simulation package utilizing TCP/IP networking to allow C and Perl based development simulation environments using Verilog or SystemC hardware models.
Black Boxes System Design and simulation with C++
tile breakout boards on a printed circuit board
Breakout boards _can_ be made by cutting off a piece of circuit board and going through the etching, drilling, solder-resist and printing process, but doing this for multiple boards quickly becomes tedious, especially if you've got to make more than a few. With v3c-eagle-tile, you can import several CadSoft Eagle .brd files and tile them onto whatever size pcb you have to hand, process them all at once and cut them apart when you're done.
Tool for store Siemens S7 PLC's data, eg: DB, DI, M and more, in a local file, or write them from local file. Include data editor.
A GDSII Viewer that reads a standard GDSII file format and displays the contents of the file in a graphical format. It allows the viewer to zoom and pan the contents of the file.
Gerber Drill IPC2581
View Gerber Files and Drill Files. View IPC-2581.
Convert C++ software programs into synthesisable Verilog using the Clang compiler frontend to parse and SystemC for intermediates.
A specialized innovative cross-platform for reverse engineering PCB's
"ReverseM" is a open-source project initiative aimed at supporting designers,researchers and hobbyists to tinker with electronics creatively. We are creating a software tool and website in spirit of reverse engineering. We are currently developing a tool that allows users to creatively convert the real-world manufactured PCB in to their respective Schematic diagrams and documenting their prototypes. Share the schematics, tinker with it to promote the electronics knowledge among interested persons. Features a) User Friendly interface for quick referencing and converting. b) Schematic View - Shows the circuit which has been converted from real world to virtual world c) PCB View - Lets you design and export the necessary documents for producing a Printed Circuit Board. d) Palette Windows - provide parts, tools and information. e) The Part Creator - a tool to modify parts or create new parts. f) Inbuilt electronic parts database. h) Quick prototyping of printed circuit boards.
PIC 16F877A Registers in one click!
PIC(R) 16F877A Reg Browser helps you to browse the large number of registers in the PIC(R) 16F877A. You just have to pick up a register name in the List Box, and get all informations about the register (Address(es), Bank(s), Configurations bits...). Author: ANDRIAMILAMINA Monge. +261 32 04 309 92 or email@example.com.
QSapecNG is a Qt-based symbolic analysis program for linear analog circuits. In fact, it consists of two indipendently parts: the SapecNG framework engine, and the application gui QSapecNG.
Icarus Verilog is an open source Verilog compiler that supports the IEEE-1364 Verilog HDL including IEEE1364-2005 plus extensions.
Hantek DSO-2150 software (Voltcraft/Darkwire/Protek/Acetech e.t.c DSO-2090/2150/2250/5200A e.t.c)