ECL is a system-level specification language for HW/SW designs and is based on Esterel and C. The ECL compiler parses ECL, writes Esterel and C, and uses the Esterel compiler to produce an implementation. Originally developed at Cadence Berkeley Labs.
An EEChip is a chip whose software can evolve. It works like Conway\'s Game of Life, but with highly generic rules for each cell. This project simulates an EEChip in C, and the chips are tested, selected, and mutated in Ruby.
Electronics design automation (EDA) suite for design of electronic circuits and systems, simulation (through physical / semi-empirical methods) and PCB layout/fabrication tools. Includes a GUI interface, Unix-style command-line utilities and a C API.
Efficient Symbolic Tools package (EST) is a BDD based tool for the formal verification of concurrent systems. Its advantages are flexibility, portability and an efficient memory management. It runs under different OS, including Linux and Windows 2000/XP.
Utilización de KTechlab para la enseñanza de la electrónica digital. Se incluyen manuales, ejercicios y ejemplos. (Using KTechlab for teaching digital electronics. They include manuals, exercises and examples).
Open Experimental CNC Tool Project for viewing and converting DXF(CAD) Files to G-Code(RS-274) NC-Files.
Experimental Boundary Scan (EBS) project provides software (driver + application) support to JTAG/IEEE 1149.1 boundary scan master (BSM) controllers under the Linux OS.
Framework for the Analysis and Modification of EDIF netlists (FAME) is a C++ framework, developed at Politecnico di Torino, aimed at automating the analysis and modification of complex circuit netlists described in the standard EDIF 2.0.0 language.
Eclipse-based plugin for HRT-HOOD and HRT-UML design for Hard Real Time Systems
This project is a collection of field solver tools.
Digital Signal Processing Block Diagram Compiler - user extendable to all DSP's, but presently supports only the TI C2000 family. Rich support for fixed point arithmetic, both saturated and unsaturated. Block diagram entry is via TinyCAD (included).
All design related files for a general purpose PCB, hosting a Microchip dsPIC33FJ256MC710 part. Includes gEDA schematic and layout files, BOM, etc... The card will include power regulation, SD memory card, in-circuit programming support, etc...
Geometric Technology - Programs written for MicroStation CAD System design automation.
Gnetman is primarily a netlist translator, capable of translating between formats such as VHDL, Verilog, and SPICE. Only structural gate-level netlists are supported. Various netlist manipulations are supported.
This is a Computer Aided Electronic Design tool. It features schematic capture, simulation and PCB layout for both analog and numerical componants with the help of Gnome.
HSP16 is a Pesona-16 (http://www.mysem.com) microprocessor simulation and development environment written in C. HSP16 is capable to simulate and run unmodified Pesona-16 assembly.
The project targets the chemical engg. students and industry as an aid to the design of heat exchanger. It will be a study aid and shall be able to give te relimnary dessign to an expert before he starts and puts his expertise into it. Design,Rating and
The idea of this project is automatize hydrogen Booster system created by Stanley Meyer to implement it in cars,trucks and electric plants as well as for production of free energy.
This is an IEEE 1532 compliant JTAG programmer for CPLDs, FPGAs and similar programmable logic devices. It is only starting; developers are welcome!
This is a project with hardware and software. It will show u an Intelligent Car based on PIC
A program to reverse engineer JEDEC programming files for PLDs (Programmable Logic Devices). The first version of this program can handle simple PAL devices. Future versions will be able to reverse engineer CPLDs (Complex PLDs).
Currently, all existing formal tools are designed to serve as formal verifiers, using one implementation or another. JTLV is a new tool aimed to facilitate and provide a unified framework to the development of formal verification algorithms.
Java Decision Diagrams (BDD) libraries: JDD and JBDD
This project used to contain two decision diagrams libraries: - JBDD: a Java interface to two popular BDD libraries, CUDD and BuDDy - JDD: a native Java library supporting BDD, Z-BDD Both projects have now been moved to bitbucket.org: - https://bitbucket.org/vahidi/jbdd/wiki/Home - https://bitbucket.org/vahidi/jdd/wiki/Home If you are wondering why the move was made after 14 years (!!) on SourceForge, I suggest you read this article: http://arstechnica.com/information-technology/2015/05/sourceforge-grabs-gimp-for-windows-account-wraps-installer-in-bundle-pushing-adware/
Open Firmware for K8056 8-Channel Relay Card
Development of open source firmware/software for K8056 8-Channel Relay Card produced by Velleman® Inc.
LTProg is pindriver technology multi devices programmer througth the PC USB Port