Open source C++ framework utilizing boost.org libraries and specialized for development of EDA applications.
A console app simulating a CNC controllable bench lathe. Drawing output into a picture, several error checking.
Crushed bee Zigbee/Ethernet project: Goal become a software-hardware reference project for Zigbee/Ethernet SCADA system.
DICaD is a free EDA software for VLSI circuits design.
The project targets the chemical engg. students and industry as an aid to the design of heat exchanger. It will be a study aid and shall be able to give te relimnary dessign to an expert before he starts and puts his expertise into it. Design,Rating and
A static timing analysis program written in C++. Cadence LEF/DEF definitions of circuit geometry and SDF definitions of circuit timing data of a synchronous circuit are compiled in order to generate timing constraints for non-zero skew circuit operation.
This project is developed for Full Customer Design Enviroment. Schematic Entry/SPICE/SPICE(RF)/Layout/Verilog-AMS Via /Verilog Via Will be included.
This is an IEEE 1532 compliant JTAG programmer for CPLDs, FPGAs and similar programmable logic devices. It is only starting; developers are welcome!
Black Boxes System Design and simulation with C++
MammCAD is a tool suite for performing rapid computer aided diagnosis of radiographic mammogram images. It is intended to be used for rapid development and deployment of low-cost CAD machines.
An Open Source Parser Library for parsing Verilog, System Verilog, EDIF and VHDL source files.
This is a program that solves the Mathematical Algorithm for the Low Power Transformer.
an open source software for electronic design automation (EDA).
OpenECAD is an open source software for electronic design automation (EDA / ECAD). OpenECAD integrates all stages of the design process: Schematic Capture, PCB layout, Component editing, CAM file generation. OpenECAD is cross-platform program, written with QT5 framework and run on Windows, Linux, and Mac OS X.
Open-source tools to assist the Low Band DXer
Provide a modern open-source set of tools to assist in the planning, construction, and operation of a Low Band (40m, 80m, and 160m) DX amateur radio station. Initial goal is to provide cross-platform functionality of ON4UN's set of tools for Microsoft 95 that can be run on many other systems. (This project is not connected with ON4UN.)
The OpenOCD-GUI project aims to reduce the needs for people who use OpenOCD (Open On-Chip Debugger) for his/her embedded project. The OpenOCD-GUI is nothing but a powerful front-end, it is not a part of OpenOCD.
Simulation Tool for Phase-Locked Loops
A simulation tool for Phase-Locked Loops with charge pump phase detectors. The tool simulates phase and frequency steps with continous reference and random bit stream reference for data clock recovery.
ParaDef (Parametric Definition System) is a complete CAD/CAE/Product Development solution. ParaDef encompasses all aspects of product development into a single IDE, enabling rapid development of new products and in-depth analysis of existing solutions.
PhiCAD is a LGPL'd , cross-platform software intended to provide to community an eclectic suite of CAD such as EDA to solve physics problems.
Generator for prefix graphs, which can be used to implement parallel prefix adders.
Call for the specifications of (next generation of spice) spice4. The concept of spice kernel is proposed. The main function of spice kernel is to provide a communication between "application layer" and "low-level Algorithm layer".
Currently, all existing formal tools are designed to serve as formal verifiers, using one implementation or another. NO tool is providing a global framework to develop algorithms. Silicis is a new formal framework for designing [verification] algorithms.
TeslaCoiler helps build Tesla Coils by solving the mathmatical aspects of one. The end results are the most useful for when your planned Tesla Coil's LC Resonance Frequencies don't match. It will adjust specific parts of tank circuit to match the secon
VeSpi is a Verilog to SPICE netlist conversion tool. It takes structural Verilog as input and produces an equivalent SPICE netlist compatible with Berkeley SPICE. This allows a designer to check analog properties of a digital logic block.
Vessel is an electrical circuit design and simulation tool designed mainly for students, hobbyists and amateurs; but also applicable in semi-professional and professional environment. It aims to be portable, extensible and easy to use.