GNU PIC LIBRARY PROJECT The interest of this project is to develop a set of Libraries that are released in LGPL License to use to PIC microcontroler programming. Then any program resulted by this use would be a proprietary or free softwares.
8051lib is a collection of easy-to-use C Functions and Assemble Languages Sets for the 8051 microcontroller. The Final Goal is to make the microcontroller developer focus on the Algorithms not the Hardware Drivers.
ElectroCat project is free version of CAD system for electrical equipment design based on TinyCAD project. Our purpose to make it industrial oriented and support Russian (CIS) standards for such kind of documentation.
The project targets the chemical engg. students and industry as an aid to the design of heat exchanger. It will be a study aid and shall be able to give te relimnary dessign to an expert before he starts and puts his expertise into it. Design,Rating and
An Open Source Parser Library for parsing Verilog, System Verilog, EDIF and VHDL source files.
This project aims at providing Open Source tools for the development and the verification of SystemC/TLM (Transaction Level Modeling) IP models, and at promoting their use by embedded software developers on SoC (System-On-Chip).
A methodology to create netlists for printed circuit board layout using a novel PCB specific HDL as the source language.
PhiCAD is a LGPL'd , cross-platform software intended to provide to community an eclectic suite of CAD such as EDA to solve physics problems.
Currently, all existing formal tools are designed to serve as formal verifiers, using one implementation or another. NO tool is providing a global framework to develop algorithms. Silicis is a new formal framework for designing [verification] algorithms.
CImmerSys is a project for make an specific supervisory and control software for controlling all the devices of a Temporary Immersion System for vitro plants production.
Application able to simplify and make calculations involving a circuit built by the user.
VeSpi is a Verilog to SPICE netlist conversion tool. It takes structural Verilog as input and produces an equivalent SPICE netlist compatible with Berkeley SPICE. This allows a designer to check analog properties of a digital logic block.
WIDI CAD is a project which tries to deliver an open source WIring DIagram CAD. In Opposit of all the other electrical CAD Systems WIDI is not meant for PCB's. It's meant for industrial control cabinets.
yaeda project aims to be a fully integrated EDA tools (from schematic entry to pcb layouting and simulation) with unique web-centric features and a web community of engineers for sharing implementation and ideas
IVI is a graphical, interactive user-interface to various Open-Source HDL simulators. IVI is transitioning to using the Eclipse application framework.