Covered is a Verilog code coverage utility using VCD/LXT/FST dumpfiles (or VPI interface) and the design to generate line, toggle, memory, combinational logic, FSM state/arc and assertion coverage report metrics viewable via GUI or ASCII format.
cad-utils is a set of modules for designing electrical boards. These programs allow you to cut and place graphs which used to present the models of the original electrical schemes.
The ThermoFluid library is a free open source physical model library for thermo hydraulic models in the Modelica modeling language.
PROJECT IS DISCUNTINUED This project is about to contain information how to write data like boot loader into various flash devices on diffrent CPUs trough JTAG interface
clk++ is a program for automated typesetting of timing diagrams in digital electronics. Output is PostScript in original, but inheritance can be used to provide both for different output formats and interactive work.
IMPORTANT: The flosslogic project has merged with the sigrok project. Development continues in the sigrok wiki, mailing lists, IRC channel, and git repository.
Virtual electronic circuit simulation with JAVA based schematic entry and wave viewer, based on (Berkeley) SPICE, for any OS/Server/Browser configuration. Due to missing public feedback for over one year its status is set to INACTIVE (1/2004) - sorry.