Ngspice project aims to improve the spice3f5 circuit simulator.
An Electronic Definition Interchange Format (EDIF) parser which allows exports from one EDA schematic capture system (such as OrCad) for import into another (such as KiCad)
ArchC is an open-source architecture description language based on SystemC. Its goal is to provide designers with a tool to evaluate new ideas in processor and ISA design, memory hierarchy, etc. and other aspects of computer architecture research.
A UNIX/X11 circuit drawing application with schematic capture. Features user-definable parts libraries and fully hierarchical SPICE netlist generation.
Verilog Finite State Machine (FSM) Code Generator
SmGen is a finite state machine (FSM) generator for Verilog. On the other hand, it is not an FSM entry tool. The input is behavioral Verilog with clock boundaries specifically set by the designer. SmGen unrolls this behavioral code and generates an FSM from it in synthesizable Verilog. Clock boundaries are explicitly provided by the designer so there is good control on the expected timing
PEP is a modelling and verification framework for parallel systems, providing a large number of different modelling languages and verification techniques (e.g. SDL, Petri nets and model checking)
AvrGui jest to program, który zajmuje się kompilacją i programowaniem kontrolerów. Wykorzystuje on kompilator avr-gcc. Zastosowanie biblioteki Qt umożliwia prace programu zarówno na systemach Linux, jak i windows.
Capsim(r) C Text Mode Kernel(TMK),DSP and communication blocks, topologies, libraries and tools for the development of high performance block diagram digital signal processing and communications systems,built in interpreter for scripting.SystemC support.
"kdiv" is a generator of routines for optimized division by an integer constant based on the work presented in H.S. Warren's "Hacker's Delight". "kdiv" can be used to emit a generic assembly or C implementation of (signed/unsigned) division.
PKtool is a SystemC/C++ environment dedicated to the power estimation for digital systems described in SystemC.
Brushless DC controller (ESC) Fully functional sensorless ESC. Uses BEMF detecton for rotor position sensing. Software trays to maintain maximum speed on currently available power(pwm duty). It works like ordinary DC motor. More load means, on same power, lower speed and higer current. Motor speed (current) PWM , direction etc. is adjustable via serial port commands. For example - press "k" button to add power, "j" button to reduce power and "t" button to reverse rotor direction etc. I have used neodymium magnets BLDC, CD drive BLDC and car generator as BLDC motor without any modification in software, hardware - it just works. Schematic is done using EAGLE PCB software Software is witten in spin langue. If You want to improve this project then put your thoughts into discussion section. Or if You have some burning information - drop me an email "firstname.lastname@example.org" enjoy,