4 projects for "network security simulator" with 2 filters applied:

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  • 1
    FlowViewer

    FlowViewer

    FlowViewer is a web-based netflow data analysis tool.

    FlowViewer provides a convenient web-based user interface to Mark Fullmer’s flow-tools suite and CMU's netflow data capture/analyzer, SiLK. The inclusion of the underlying SiLK tool set enables FlowViewer users to continue to use the tool with the newer IPFIX netflow data protocol, which includes support for IPv6 and Cisco's v9 and FNF netflow. FlowViewer has been developed for NASA’s Earth Sciences Data and Information System (ESDIS) networks, and credit goes to NASA for their usual...
    Downloads: 4 This Week
    Last Update:
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  • 2
    Network Simulator (fork CORE - Live USB)

    Network Simulator (fork CORE - Live USB)

    Live DVD with CORE network simulator

    The Common Open Research Emulator (CORE) is a tool for emulating networks on one or more machines. You can connect these emulated networks to live networks. CORE consists of a GUI for drawing topologies of lightweight virtual machines, and Python modules for scripting network emulation.
    Downloads: 4 This Week
    Last Update:
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  • 3
    steganoroute

    steganoroute

    Send steganographed text messages to mtr with fake hops in the network

    Steganoroute is a tool to send steganographed text messages to another computer over the network. The receiver must make a traceroute to the sender using the mtr program (and pressing 'd' once to switch the display mode to the continuous graph). This tool, the sender, creates several fake hops and makes them answer the ICMP packets (or not) to write the letters one by one on the mtr client screen.
    Downloads: 0 This Week
    Last Update:
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  • 4

    ASDM-NoC

    Asynchronous Spatial Division Multiplexing Router for On-Chip Networks

    This project provide a reconfigurable asynchronous SDM router which can be configured into a basic wormhole router or an SDM router with multiple virtual circuits in every direction. Features: * 5-port router for mesh network (0 south, 1 west, 2 north, 3 east, 4 local) * The dimension order routing (XY routing) * Available flow control methods: wormhole, SDM, VC * Reconfigurable number of virtual circuits, buffer size, data width * Fully synthesizable router implementation * SystemC testbench provided Languages: * Routers are written in synthesizable SystemVerilog * Test benches are provided by SystemC Software requirements: * The open source Nangate 45nm cell library * Synopsys Design Compiler (Synthesis) * Cadence IUS -- NC Simulator (for SystemC/Verilog co-simulation)
    Downloads: 0 This Week
    Last Update:
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