Showing 3 open source projects for "simulation"

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  • 1

    DEC routing protocol for WSN

    A Deterministic Energy-efficient Clustering protocol for WSN

    ...We propose a deterministic energy-efficient clustering protocol that is dynamic, distributive, self-organizing and more energy efficient than the existing protocols. It utilizes a simplified approach which minimizes computational overhead-cost to self-organize the sensor network. Our simulation result shows a better performance with respect to energy consumption, which is reflected in the network lifetime in both homogeneous and heterogeneous settings when compared with the existing protocols. It is worthy of note that our approach approximates an ideal solution for balanced energy consumption in hierarchical wireless sensor networks.
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  • 2

    Enhanced Stable Election Protocol- SEP-E

    An enhanced stable election protocol for wireless sensor network

    ...Clustered techniques have since been employed to optimize energy consumption in this energy constrained wireless sensor networks. We propose an Enhanced-SEP clustering algorithm in a three-tier node scenario to prolong the e ffective network life-time. Simulation results shows that the Enhanced-SEP protocol achieves better performance in this respect, compared to other existing clustering algorithms such as LEACH and SEP in both heterogeneous and homogenous environments.
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  • 3

    ASDM-NoC

    Asynchronous Spatial Division Multiplexing Router for On-Chip Networks

    ...Features: * 5-port router for mesh network (0 south, 1 west, 2 north, 3 east, 4 local) * The dimension order routing (XY routing) * Available flow control methods: wormhole, SDM, VC * Reconfigurable number of virtual circuits, buffer size, data width * Fully synthesizable router implementation * SystemC testbench provided Languages: * Routers are written in synthesizable SystemVerilog * Test benches are provided by SystemC Software requirements: * The open source Nangate 45nm cell library * Synopsys Design Compiler (Synthesis) * Cadence IUS -- NC Simulator (for SystemC/Verilog co-simulation)
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