Search Results for "systemverilog"

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Showing 1 open source project for "systemverilog"

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    HDL Checker

    HDL Checker

    Repurposing existing HDL tools to help writing better code

    HDL Checker is a language server that wraps VHDL/Verilg/SystemVerilog tools that aims to reduce the boilerplate code needed to set things up. It supports Language Server Protocol or a custom HTTP interface; can infer the library VHDL files likely to belong to, besides working out mixed language dependencies, compilation order, interpreting some compiler messages and providing some (limited) static checks.
    Downloads: 0 This Week
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