Search Results for "timing"
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Showing 2 open source projects for "timing"
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SpinalHDL
Scala based HDL
...Because SpinalHDL is embedded in Scala, it allows reuse of functional abstractions, parameterization, modular composition, and higher-level constructs to manage complexity. It supports building systems at various levels—single modules, pipelines, memories, controllers, etc.—while letting the designer control timing, pipelining, and resource sharing explicitly. The generated hardware can be synthesized for FPGAs or ASIC flows, making it practical for real designs. -
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ALCHA
A New Programming Language for FPGA Projects
ALCHA aims to reduce FPGA project develop time by means of automation and abstraction, but without loosing the low-level control that HDLs, such as Verilog, provides. It will support an object oriented programming model, abstract data and signal types, and compile-time scripting.
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