upf2cpf is a cool command line tool which will takes in a UPF(Unified Power Format) and will convert it to a CPF(Common Power Format).This tool is very useful for Chip Design Engineers, who want to feed the power related info about the RTL in UPF/CPF.
This project includes 2 parts: the open FPGA+DSP architecture for the GPS hardware and the GPS software running in embedded system and PC
The RoboCup Team of Shanghai University (aka. Strive Team) is now devoting itself to the Humanoid League Contest. Many features like machine vision, pace generation, speech cognition, etc. of the humanoid robots is rising here in the following years.
Make your own virtual FPGA system and profile deeply with CI.
TestDrive Profiling Master is a free simulation software for Verilog/SystemVerilog and C/C++. It supports a CI (Continuous Integration) activity for H/W & S/W engineers' cooperation. Run by MS Windows environment, its use is governed by MIT License(Profiles) and LGPLv3(TestDrive Profiling Master). Based on the powerful compiler Verilator and GCC, TestDrive Profiling Master provides a totally free virtual FPGA system environment with various dynamic documents for profiling in deep on your system design. It performs a seamless conversion to a real FPGA environment without any changes of your testing software. I hope you will accomplish a successful design with TestDrive Profiling Master. Q&A : firstname.lastname@example.org
Scicos-HDL is a tool to design digital circuit system; it integrates the hardware circuit, algorithm and Scilab/Scicos environment as a plat for digital circuit design, simulation and Hardware Description Language generation. ZhangDong & KangCai