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Showing 7 open source projects for "synopsys"
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Our robust pre-built connectors and our no-code, drag-and-drop interface makes it easy and fast to automatically sync vendors, invoices, and invoice payment data between Tipalti and your ERP or accounting software.
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BigQuery Studio provides a single, unified interface for all data practitioners of various coding skills to simplify analytics workflows from data ingestion and preparation to data exploration and visualization to ML model creation and use. It also allows you to use simple SQL to access Vertex AI foundational models directly inside BigQuery for text processing tasks, such as sentiment analysis, entity extraction, and many more without having to deal with specialized models.
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SVUnit
Systemverilog Unit Test Framework
SVUnit is a unit test framework for developers writing code in systemverilog. Verify systemverilog modules, classes and interfaces in isolation with SVUnit to eliminate bugs before they infest your design! -
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*** NOTE: as of Sept 2012, Synopsys is no longer using this project to update GNU Toolchain and Linux kernel for DesignWare ARC processors. Open Source Software for DesignWare ARC processors has been moved to github at: https://github.com/foss-for-synopsys-dwc-arc-processors
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ASDM-NoC
Asynchronous Spatial Division Multiplexing Router for On-Chip Networks
... testbench provided Languages: * Routers are written in synthesizable SystemVerilog * Test benches are provided by SystemC Software requirements: * The open source Nangate 45nm cell library * Synopsys Design Compiler (Synthesis) * Cadence IUS -- NC Simulator (for SystemC/Verilog co-simulation) -
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This is the public release of code for the Synopsys Ottawa SNUG presentation "ICC Tips and Tricks" by Chris Krueger on September 28 2010
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Venn is a secure workspace for remote work that isolates and protects work from any personal use on the same computer. Work lives in a secure local enclave that is company controlled, where all data is encrypted and access is managed. Within the enclave – visually indicated by the Blue Border around these applications – business activity is walled off from anything that happens on the personal side. As a result, work and personal uses can now safely coexist on the same computer.
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Verilog 2005 synthesizable subset parser built on ANTLR framework. 3-nov-2014: latest release here: https://github.com/gburdell/parser
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The RegWorks(TM) is a set of tools intended to automate the process of register class creation directly from the design specification. It can also be used with other third party tools such as Synopsys RAL or equivalent.
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An online SSL (128-bit strong encryption) repository for scripts created and maintained by Synopsys Design Consultants.
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