Search Results for "electronic simulation" - Page 6

vIDE is a cross-platform tool for writing and simulating Verilog models. It provides user friendly project management and file editing, integrated simulation engine, waveform viewer, pre-compiled modules, and many other cool features.

Provide a set of circuit design wizards to assist in electronic design. The wizards should initially provide a graphical output of the circuit, the values of components and a SPICE netlist for simulation. This project is in the early stages.

KIDESIM will be a fully featured cross manufacturer development and simulation environment for the creation of embedded microcontroller solutions.

Elenix is a GNU/Linux distribution dedicated to the needs of management, development, and troubleshooting of electronic circuits.

Magnetostatic finite differences simulation tool based on GNU Octave and a Perl/Tk user interface.

Tool-independent Makefile generator for VHDL models.

Lithoguru is oriented to free and simple lithography simulation. It helps to develop user defined models. The final goal will include OPC and PSM automation.

NecJGui is an antennas design tool, interface for Numerical Electromagnetic Code. It allows easily making NEC input files, and viewing them in 3D. It also contains a version of the simulator, so it's complete IDE for full-wave EM simulation.

jEDA IDE (Java Eletronic Design Automation Integrated Development Environment) is a multiplatform, open-source tool used for electrical circuit design, schematic capture, simulation and prototyping.

PowerLab is an open-source, client-side computational engineering workbench for distributed clean energy systems. It delivers deterministic mathematical engines for solar photovoltaic array sizing, battery storage (BESS) runtime with dynamic Peukert capacity derating, and power inverter surge capacity modeling. Key Features: - Solar PV seasonal tilt optimization, temperature derating, and NREL SAM validation. - Battery storage discharge runtime with dynamic Peukert capacity loss...

The aim of the UVE project is to create software that automatically generates a verification testbench (TB) written in SystemVerilog (SV) and integrating the UVM methodology. UVE makes the rapid development of a verification environment a simple process. The generated TB is directly able to perform random actions on the DUV (design under verification). For this UVE provides a graphical user interface, a code generator, compilation scripts and a library of verification IPs (VIP). One of...

Labcoat for SuperWikia Alpha fabrication manages new or revised fabrication processes. Its 'Cleanroom' applets allow codesmiths to access the lab environment, used to create semiconductors, substrate prototypes, chipset instruction blocks and other Labcoat projects. Our extensions in future releases will include UML support for C#/C++ conforming projects, import/export architecture schematics and refactoring sub-projects.