Search Results for "eda" - Page 18
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Showing 545 open source projects for "eda"
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IC CAD tools, documentation, scripts, and libraries for designing high-performance ICs, including SUE for schematics, MAX for layouts, DPC for datapaths and MCC for megacells. Prebuilt binaries for Linux, Sparc-Solaris, and HP-PA.
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Call for the specifications of (next generation of spice) spice4. The concept of spice kernel is proposed. The main function of spice kernel is to provide a communication between "application layer" and "low-level Algorithm layer".
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Language used: c++ Libraries used: fltk OS: Linux Problem Description: Jtag management software for CPLD and jtag aware chips Major features: X11 UI, c++ platform for jtag apps Data formats: jtag, bsdl, binary Derived from existing project "jtag"
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VSTGL is a graphical editor for Signal Transition Graphs (STG) and Petri nets. VSTGL is able to export the created STG to Petrify - an advanced tool for analyzing and optimizing STG's - or run Petrify on the graph directly.
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Z88 a free finite elements program featuring 20 different element types for LINUX and Windows. Includes two solvers, a mesher, plot programs and a GUI with online help.
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toolbox with information and programs for Computer Aided Innovation The scientific background of Skidbladnir is known as the Theory of Inventive Problem Solving; in English abbreviated as TIPS or TRIZ, in German as TRIS.
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ATEProg is project to write software which can program AT89xx and AT89x051 microcontroler chips (and others) in ATE2000 programer (and others).
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A static timing analysis program written in C++. Cadence LEF/DEF definitions of circuit geometry and SDF definitions of circuit timing data of a synchronous circuit are compiled in order to generate timing constraints for non-zero skew circuit operation.
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CircuitSmith
Electronics Design Software
CircuitSmith is to be a comprehensive electronic design package being developed in Java which will include schematic capture, printed circuit board layout and any other features which I (and hopefully others) can be bothered to program. -
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Spgmr08 is a Linux software package for programming devices in the Motorola MC68HC908 microcontroller family.
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Integrated suite of engineering tools focusing on automation, portability, collaboration, and data management
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Provides a GPL'd test suite for verification of the verilog language. This project is affiliated with the Icarus Verilog compiler effort at icarus.com, and test reports are collected from that project.
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The Boolean Expression Reducer provides the user with various tools to visualize and analyze boolean expressions. Given an expression, it also reduces it to its Sum of Products and Product of Sums form.
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gSXprog is used with the Parallax SX-Key or SX-Blitz to program Ubicom (formerly Scenix) SX microcontrollers.
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XAvrTools is an open source graphical frontend for development with Atmels AVR microcontrollers using the UISP download tool and the AVR-GCC C compiler for LINUX. It is written in C++ using KDevelop and the QT library. It will include a software wizard.
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ESOMA is a component orientated framework for simulation and evaluation of arbitrary microprocessor and DSP architectures. Simulators using ESOMA are runtime configurable. Architectural changes do not need recompiling. Programming language is C++ (Linu
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Bobware tool suite is a set of small EDA tools which are useful in the design of integrated circuits. The suite contains a perl/tk script for region planning large ASICs (application specific integrated circuits.)
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KFilter is an application to design acoustic hifi loudspeakers in a theoretical way. It provides an interactive analysis of the equivalent analogue circuit design.
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DGC is a tool for the creation of digital netlists. DGC does an optimization and technology mapping for an abstract description of boolean functions and state machines. Output formats are EDIF, XNF and VHDL. Input formats are KISS, PLA and others. See also: http://gitorious.org/dgc-gtk/
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ViPEC is an network analyser for electrical networks. It takes a schematic description of an electrical network, and performs a simulation of the circuit response in the frequency domain. Output is in the form of port parameters (S, Y and Z).
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RSTK is a C language program that generates Reed-Solomon HDL source code modules that can be compiled and synthesized using standard VHDL or Verilog compilers and synthesis tools.
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Netsim is a mobile ad hoc network simulator targeted at large heterogeneous node configurations. It is written in Java and is easily extensible through its modular concept.
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C++ template classes for Multi-Value Logic support arbitrary precision and user defined Multi-Value Logic types. This library comes with pre-defined data types: integer, boolean, bit, logic, std_logic, bit_vector, logic_vector and std_logic_vector.
