Search Results for "state machine" - Page 13
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Showing 355 open source projects for "state machine"
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Aleph is both a multi-platform machine learning framework aimed at simplicity and performance, and a library of selected state-of-the-art algorithms.
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MelaJò Portal Framework is a framework to develop Java Enterprise/J2EE/MVC based applications rapidly and easily. It's based on Finite State Machine concept. It's used for years to create real business web applications with J2EE architecture.
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Aqueduct is a simple state machine library written in Java. Some programs can be described naturally as a state machine or a flowchart; this library is intended to simplify the development of such programs.
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A generic finite state machine (FSM) API for the Java platform. The API enables creating a performing FSM at runtime and with type safety. Project also includes a non-blocking context scheduler for running FSMs over multiple contexts.
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Tool used to generate state machine framework code from a terse set of directives embedded directly in the input source code file. This tool will also generate GraphViz graphical description and Spin/Promela modelling output.
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dia2fsm reads DIA diagram files constructed in the prescribed format and produces Finite State Machine (FSM) skeleton code. dia2fsm currently supports code generation to C and C++ and is built on Linux only. dia2fsm depends on Qt, and has been partially
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FSMGenerator is a turn-key solution for FSM (Finite State Machine) automatic generation and integration within user`s software. Please, register to get fast personalized support. Feedbacks, feature requests and bug reports are greatly appriciated.
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Many design artifacts can be directly executed. UML state processes can be executed by a state machine; UML sequence diagrams can be executed directly. ExecDesign will be a suite of Java tools which can be used to document and execute UML designs.
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When running multiple domains through the Xen hypervisor, this library will allow a privileged domain to view the runtime state of another domain. This technique is known as virtual machine introspection.
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jStates is a java library for easy state machine design and implementation.It uses XML to define states and state transitions. jStates is aimed at easy integration with desktop J2SE applications, Struts, Commons Validator, Web and other J2EE technologies
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This is an Hierarchical State Machine (aka Statechart) engine written in Java (1.5 +) Actually we will develop only support for a subset of UML 2.0 semantics but, in future, we hope to add support for other semantics.
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NState is a pragmatic Finite State Machine implementation in DotNET. FSMs are defined either in XML or programmatically, and can be run directly or compiled to either C# or VB.NET. Includes WinForms and ASP.NET Panels, and Visual Studio integration.
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FSMExplorer - Finite State Machine Explorer after reading specification of N FSM entities, generates available states for this FSM.
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Hierarchical State Machine Framework. Published in December 2005 issue of C/C++ User's Journal: http://www.ddj.com/184402040
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Firebolt Network library (fnl) is a high level framework for network protocol implementations. You can implement your finite state machine oriented network protocol without messing with sockets. Define your states,events,transitions and you're ready.
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Blackbadger is a distributed ANT runtime for controlling and running tests against a large array of machines without complicated setup. Self-discovery and full Apache Ant integration, Blackbadger provides a distributed state machine.
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Long Activity Workflow is a activity based workflow(finit). It use activity (condition) to determine which state to go. The aim of LongAWF is to use it like a automatic machine.
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JSpasm is a pure Java package for developing event-driven, state-based software applications and packages. This small-footprint package will handle multiple models and large numbers of entities in parallel, and includes features to support SMP operation.
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qf4net: Quantum Framework for .Net Hierarchical State Machine and Active Objects by Dr. Rainer Hessmer
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Cellogica is a cellular logic analysis tool. It incorporates sequential logic and finite state machine to elucidate the relationship between transcription factors and corresponding gene expression.
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StEAM, (State Exploring Assembly Model Checker) is a model checker for native concurrent C++ programs. It extends a virtual machine - called ICVM - to perform model checking directly on the assembly level.
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lsx is a small and powerful text and source code generator based on a format called Eva. Both java libraries for lsx and Eva and tutorial with some "Hello" samples including "Hello State Machine", interesting demo that generates C++ code.
