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This project aim to develop a suite of tool to ease the development of ASIC/FPGA solution. The final program should be an IDE enabling the creation and specification of a project from it's start to finish.
the goal of this project is to build a stack for Lonworks Protocol and device working on this protocol
The RoboCup Team of Shanghai University (aka. Strive Team) is now devoting itself to the Humanoid League Contest. Many features like machine vision, pace generation, speech cognition, etc. of the humanoid robots is rising here in the following years.
You’ve likely added a tool to fix one problem and then a different tool to fix another problem. Pretty soon you have multiple instances of the same tool, different tools with overlapping functionality, no ability to collaborate across teams—all resulting in unknown bottlenecks and complicated or no reporting. As a DevOps leader, it’s up to you to balance the autonomy and flexibility of a DevOps approach. But how?Sponsored Listing
What would verilog code translated to unlambda look like? This question has puzzled me for a long time and I've decided to do a unlambda backend to my c->verilog compiler. Come to think of it, why stop at unlambda? I will go all the way to NAND gates.
CRC Generator is a command-line application that generates Verilog or VHDL code for CRC of any data width between 1 and 1024 and polynomial width between 1 and 1024. The code is written in C for Win32, bus easily portable for other platforms