Join ACM and take advantage of thousands of online courses, video tutorials, and online books available through ACM’s online Learning Center. Stay ahead of the curve by reading Communications of the ACM, our monthly flagship publication that delivers incisive essays, reviews and research, and ACM Queue, an online magazine for software developers written by leading software engineers, computing researchers and tech entrepreneurs.Sponsored Listing
- Audio & Video
- Business & Enterprise
- Home & Education
- Science & Engineering
- Security & Utilities
- System Administration
Scanning Probe Microscopy Controller and Data Visualization Software5 weekly downloads
GIAnT (Generic Implementation ANalysis Toolkit) is a platform for physical analysis of (embedded) devices. Primarily designed for hardware security analyses, it is built around an FPGA-based board for fault injection and side-channel analysis. This project has been supported by the German Federal Ministry of Education and Research BMBF (grant 01IS10026A, Project EXSET).1 weekly downloads
Verilog Finite State Machine (FSM) Code Generator
You’ve likely added a tool to fix one problem and then a different tool to fix another problem. Pretty soon you have multiple instances of the same tool, different tools with overlapping functionality, no ability to collaborate across teams—all resulting in unknown bottlenecks and complicated or no reporting. As a DevOps leader, it’s up to you to balance the autonomy and flexibility of a DevOps approach. But how?Sponsored Listing
HW(VHDL) and SW of logic analyzer and On-Chip-Verification(OCV) for Value Change Dump(VCD) file format that exported to seemd SystemC ,ModelSIM, and many other EDA tools. Very easy and Simple.
Common Lisp frontend to Verilog HDL -- use the Common Lisp macro system to generate reams of boring, ugly Verilog.
zuphinx (say zoo'finks) is an efficient VHDL design environment.