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PID_control, real_time, matlab_simulink, xilinx_ise, fpga_spartan3e2 weekly downloads
Asynchronous Spatial Division Multiplexing Router for On-Chip Networks
CoreTML framework is an open-source template-based configuration system allowing the developer to create parametrized templates by inserting special content to any text files. Its main purpose is to serve as a toolkit for semiconductor IP core creation (based on VHDL/Verilog).
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Frupo stands for Frugal Processor. The idea is to create a small footprint,implementation independent,soft core optimized for easy C programming. The project involves creation of the core itself as well as a toolchain to support it.
Verilog Finite State Machine (FSM) Code Generator
Please see https://sourceforge.net/projects/smpla/?source=directory