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This is a collection of tools and a code library to assist engineers who are developing SystemVerilog based verification environments. Components include utility libraries, scoreboard and shutdown manager implementation, register tool, etc.2 weekly downloads
Holds all information related to creating an Agile Development Methodology geared towards ASIC/FPGA Verification.
Bluespec SystemVerilog Eclipse Plugin
Tool-independent Makefile generator for VHDL models.
WiFi for machines based on the 65xx CPU family.
The project uses the infrared camera from the wiimote to track hand gestures. This tracking is performed on an Altera DE2-70 FPGA
Wireless Sensor Node sniffer hardware front-end and GUI
This library supports interoperability between components written for different verification methodologies such as VMM and OVM. This is maintained by the Accellera Verification Intellectual Property Technical Subcommittee.1 weekly downloads