Hdot264 is an experimental video codec project that is compliant with the latest and most efficient video compression standard. That standard has many aliases, including H.26L, JVT, MPEG-4 part 10, AVC and H.264 .
This project implements a reduced instruction set (RISC) CPU in VHDL. It was designed for the Altera Flex10k20 chip, but the VHDL code should port to any compatable chip. The instruction set is extensive, and the design is easily extendable to 16 bits.