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HDL Checker is a language server that wraps VHDL/Verilg/SystemVerilog tools that aims to reduce the boilerplate code needed to set things up. It supports Language Server Protocol or a custom HTTP interface; can infer the library VHDL files likely to belong to, besides working out mixed language dependencies, compilation order, interpreting some compiler messages and providing some (limited) static checks. Notice that currently, the unused reports has caveats, namely declarations with the same name inherited from a component, function, procedure, etc.

...Linting can be controlled via the user configuration. In VS Code, this is settings.json. To control the visibility and severity of the diagnotics, there are a number of lists that can be set in the user configuration which make use of each diagnostic's error code. During analysis language server produces Python code from compiled modules and builtins which is similar to Python module stubs. It may also produce database files holding module analysis for faster retrieval later.