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Top Apps

  • Trial SolarWinds Backup and you could receive a free Amazon Echo Dot Trial SolarWinds Backup and you could receive a free Amazon Echo Dot Icon
    SolarWinds Backup provides lightning-quick recovery that can restore business continuity after a disaster. For a limited time only, when you try SolarWinds Backup and store at least 100GB of selected data, you have the chance to receive a free Amazon Echo Dot.
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    The Smarter Business Phone Solution

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  • Icarus Verilog

    Icarus Verilog is an open source Verilog compiler that supports the IEEE-1364 Verilog HDL including IEEE1364-2005 plus extensions.

  • Free tools and cores for FPGAs

    Tools for FPGA development and IP cores. This project provides tools, cores and documentation to develope FPGA applications. The project focuses on VHDL.

  • ghdl-updates

    GHDL - a VHDL simulator

    GHDL is the leading open source VHDL simulator. *** Now on *** We have binary distributions for Debian Linux, Mac OSX and Windows. On other systems, getting GHDL from here means downloading the current source package and building GHDL from source. Alternatively you can get the latest source version (warning : occasionally unstable!) by pulling a snapshot from the git repository.

  • adms Icon


    ADMS is a code generator that converts electrical compact device models specified in high-level description language into ready-to-compile c code for the API of spice simulators. Repository migrated to: For checkout do: git clone

  • pyrpl

    PyRPL turns your Red Pitaya into a powerful analog feedback device.

    The Red Pitaya is a commercial, affordable FPGA board with fast analog inputs and outputs. This makes it useful for quantum optics experiments, in particular as a digital feedback controller for analog systems. Based on the open source software provided by the board manufacturer, PyRPL (Python RedPitaya Lockbox) implements many devices that are needed for optics experiments with the Red Pitaya. PyRPL implements various digital signal processing (DSP) modules (see features below). It allows to arbitrarily interconnect the available DSP modules and retrieve signal values on timescales below 1 ms. The graphical user interface (GUI) provides a realtime display of the various measurement instruments and allows the easy configuration of DSP signal chains and feedback controllers. At the highest abstraction level, arbitrary feedback sequences can be defined to fulfill tasks as complex as approaching and locking a resonance of a high-finesse Fabry-Perot cavity (tested up to finesse=100,000).

    Downloads: 48 This Week Last Update: See Project
  • Get your Apps to customers 5x faster with RAD Studio. Get your Apps to customers 5x faster with RAD Studio. Icon
    Get your Apps to customers 5x faster with RAD Studio. Icon

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  • VeriWell Verilog Simulator

    VeriWell is a full Verilog simulator. It supports nearly all of the IEEE1364-1995 standard, as well as PLI 1.0. Yes, VeriWell *is* the same simulator that was sold by Wellspring Solutions in the mid-1990 and was included with the Thomas and Moorby book

  • FSMDesigner Icon


    FSMDesigner is a C++ based implementation for a Finite State Machine (FSM) design tool with integrated Hardware Description Language (HDL) generation. FSMDesigner4 uses the Simple-Moore FSM model guaranteeing efficient fast complex control circuits.

    Downloads: 10 This Week Last Update: See Project
  • Pulse Programmer Icon

    Pulse Programmer

    A programmable signal generator and RF synthesizer for scientific experiments, especially quantum computing and quantum information processing. It includes hardware, firmware, software, and documentation, all under an open source license.

  • Verilog Tool Framework

    vrq is verilog parser that supports plugin tools to process verilog. Current plugins include tools to perform x-propagation and to auto build hiearchy.

    Downloads: 6 This Week Last Update: See Project
  • AVRILOS Icon


    Simple AVR OS

    An Embedded System simple Operating System Framework that allows rapid development of applications build for AVR family but can be ported to other architectures easily enough. System is Round-Robin Co-operative multitasking. Supports: UART, SysTick Timer, ADC, SPI, EEPROM, PWM. Also supports: Xilinx FPGA configuration, FPGA SSI interface, smart card reader etc. Tested partially (different modules in each case) on ATMega163/16/32/323/8. Additionally tools for converting FPGA bitstreams to C table are provided.

  • Get the most out of your virtual environment. Get the most out of your virtual environment. Icon
    Get the most out of your virtual environment. Icon

    Monitor VMware® vSphere® and Microsoft® Hyper-V® environments from one screen. Rule your VM environment with SolarWinds® Virtualization Manager.

    SolarWinds Virtualization Manager (VMAN) provides VMware vSphere and Microsoft Hyper-V performance monitoring in a single pane of glass. Use built-in management actions to instantly remediate virtualization issues. VMAN also features PerStack ™, helping you accelerate identification of root cause by dragging-and-dropping VM performance metrics on a common timeline for immediate visual correlation across all your VM data. Try it free for 30 days!
  • FREE_VHD_Lib

    A free VHDL IPs for general purpose FPGA developpement. Need GRLIB to work properly, to setup see README.

    Downloads: 5 This Week Last Update: See Project
  • FPGA-Based Oscilloscope

    Oscilloscope components, including 100MHz quad A/D, VHDL code for Xilinx FPGA, and driver for Octave or Matlab.

    Downloads: 4 This Week Last Update: See Project
  • crc-gen-verilog-vhdl

    CRC Generator is a command-line application that generates Verilog or VHDL code for CRC of any data width between 1 and 1024 and polynomial width between 1 and 1024. The code is written in C for Win32, bus easily portable for other platforms

    Downloads: 4 This Week Last Update: See Project
  • Project 2306 IDE Rad MacOS MCU DeveR Icon

    Project 2306 IDE Rad MacOS MCU DeveR

    Electronic design and programming tools suite like Eagle, MpLab

    Currently Only MacOS is Present, PreAlpha means not Ready to use, Application is provided Without Strict Garantee, License not OSI. All others platform Windows, Linux, HaikuOS STILL under TEST, Dummy "Hello world" is provided instead Project2306 IDE : Application pour la programmation de Microcontroleurs et d' Application Electronique Project2306 IDE : for All whom want to Create and Develop on Embed Platform Software as Programming Tools suite and PCB Design Planned Features : Similar with mainstream market tools IDE and GUI Wrapper like : LabView©, Proteus©, MPLab©, Eagle CAD©, Tools Suite for Most Market Microcontroller. Tools suite for Arduino, Pinguino, Pic, AVR, ARM, Basic Stamp, Risc, other platform Fully Integrated IDE. Adobe PDF Help section SQL Connectivity Community Avail :

    Downloads: 3 This Week Last Update: See Project

    A Development Framework for Coldfire

    Contains a framework for Coldfire MCUs like 52254. The framework supports a Command Line Interface (CLI) that may work from Serial port, USB or ENET. The framework uses Processor Expert and IDE requirement is MCU Eclipse 10.4 from Freescale. Includes the FunkOS Realtime Operating System by Funkenstein Software Consulting, available at Mainly it is a support package for the development board Perseus, but I have ported also the RTOS to MCF52233DEMO board. More to come....

    Downloads: 2 This Week Last Update: See Project
  • MatlabSimulink2CPP

    Demo of Simulink to C++ C or HDL FGA for HFT potential

    Video and files download for Visual trading idea to C++ or FPGA HFT Meetup File download sample: test model (Matlab 2014b with Visual Studio 2013 C++ project generated) Powerpoint MATLAB SIMULINK

    Downloads: 2 This Week Last Update: See Project
  • MiniLA - logic analyzer SW & HW

    MiniLA logic analyzer software and hardware

    Downloads: 2 This Week Last Update: See Project
  • SystemC Logic Analyzer

    HW(VHDL) and SW of logic analyzer and On-Chip-Verification(OCV) for Value Change Dump(VCD) file format that exported to seemd SystemC ,ModelSIM, and many other EDA tools. Very easy and Simple.

    Downloads: 2 This Week Last Update: See Project
  • VHDT Icon


    VHDL Design Tool - code generation and project management

    Application simplifies the development and management of VHDL projects. The project is displayed in a well-arranged tree structure depending on the hierarchy of entities. It also helps to maintain projects in a consistent state. Other features include automatic generation of VHDL testbenches and structures based on user-defined templates. The NetBeans platform is used as a basis for the implementation.

    Downloads: 2 This Week Last Update: See Project
  • verilog compiler

    A verilog language compiler written using Java and JavaCC. It produces a netlist, an ascii text file, of all the cell connections. It can compile very large circuits comprised of many modules.

    Downloads: 2 This Week Last Update: See Project
  • ASDM-NoC

    Asynchronous Spatial Division Multiplexing Router for On-Chip Networks

    This project provide a reconfigurable asynchronous SDM router which can be configured into a basic wormhole router or an SDM router with multiple virtual circuits in every direction. Features: * 5-port router for mesh network (0 south, 1 west, 2 north, 3 east, 4 local) * The dimension order routing (XY routing) * Available flow control methods: wormhole, SDM, VC * Reconfigurable number of virtual circuits, buffer size, data width * Fully synthesizable router implementation * SystemC testbench provided Languages: * Routers are written in synthesizable SystemVerilog * Test benches are provided by SystemC Software requirements: * The open source Nangate 45nm cell library * Synopsys Design Compiler (Synthesis) * Cadence IUS -- NC Simulator (for SystemC/Verilog co-simulation)

    Downloads: 1 This Week Last Update: See Project
  • ApproxAdderLib

    Library of Approximate Adders

    We provide MATLAB and Verilog Models of GeAr, and previously proposed adders (ACA-I, ETAII, ACA-II and GDA) at GeAr is a low latency Generic Accuracy Configurable Adder that provides a higher number of potential configurations compared to state-of-the-art approximate adders, thus enabling a high degree of flexibility and trade-off between performance and output quality. These MATALB and Verilog models can allow software programmer as well as hardware designers to evaluate their code and design. To the best of our knowledge, this is the first open-source library of approximate adders that facilitates reproducible comparisons and further research and development in this direction across various layers of design abstraction. This work is a result of collaborative effort between Chair for Embedded Systems (CES) at Karlsruhe Institute of Technology (KIT), Germany and Vision Image and Signal Processing (VISpro) Lab at SEECS-NUST, Pakistan.

    Downloads: 1 This Week Last Update: See Project
  • Controlix Icon


    An operating system written in RTL

    The Controlix operating system is written in RTL and is designed to be modular, synchronous, distributed, verifiable and retargetable.

    Downloads: 1 This Week Last Update: See Project
  • FALCON Object Recognition System

    This is the award-winning FALCON I object recognition system! Capable of tracking up to 12 different objects simultaneously, and with over 6 times the raw resolution of the CMUCam, this is one of the most powerful vision systems in its class.

    Downloads: 1 This Week Last Update: See Project
  • PLP

    Powerfull pre-processor

    Powerful Verilog Preprocessor. PLP stands for Perl Pre-processor. Perl is used as "control language" that is embedded in the Verilog code (or any other code) to generate code on the fly. It is used commonly as a Verilog pre-processor but can be used with any target/output language (C, C++, Java, VHDL, plain text etc)

    Downloads: 1 This Week Last Update: See Project
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