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This project is the video controller of commodore 64 embedded in FPGA1 weekly downloads
Compiler-like program that checks Verilog source for common design errors. This tool can help beginning Verilog programmers who aren't aware of common design pitfalls and advanced Verilog programmers who want to double check large projects.1 weekly downloads
Please see https://sourceforge.net/projects/smpla/?source=directory1 weekly downloads
SystemVerilog module to substitute Verilog PLA system tasks.1 weekly downloads
upf2cpf is a cool command line tool which will takes in a UPF(Unified Power Format) and will convert it to a CPF(Common Power Format).This tool is very useful for Chip Design Engineers, who want to feed the power related info about the RTL in UPF/CPF.
Configurable VHDL bitcoin miner that is AXI4 lite compliant
This project is an Adaptive LMS Equalizer / Filter implementation with piplined architecture for speedier performance.This project implements equalizer in VHDL so can be used with FPGA/CPLD
Holds all information related to creating an Agile Development Methodology geared towards ASIC/FPGA Verification.
An arbitrary waveform generator (AWG) is a piece of electronic test equipment used to generate any arbitrarily defined electrical waveform as it's output. This waveforms can be generated with MATLAB.
Bluespec SystemVerilog Eclipse Plugin
a micro processor 16 bits optimized to hold in a CPLD
Custom uav is a complete flight control system in development. The project includes everything required for unmanned flight.
Multimedia communications require efficient and real-time implementations of multirate digital signal processing systems.
We are currently working with professors Bruce Land and Paul Kintner to develop a hardware mobile GPS receiver on an FPGA, capable of receiving L1 civilian GPS signals in real time.
Simple signal processing projects in Scilab and Matlab
This is a hardware project which create LCD matrix driver for DSTN type LCDs. Written using Xilinx WebPack.
The decimation Tools Set (DTS) generate automatically efficient implementations of Linear Feedback Shift Registers (LFSRs) in both software and hardware.
A Decimal Counter written in VHDL controlled by some buttons.
This is the source code for examples from my blog at http://wburris.com/
Simple CPU for education
Embedded Co-Design @ University of West of England Members: Matthew Browne
Automatic build management for VHDL and Verilog projects. The automatic dependency resolver finds the exact subset of sources, and the correct order they must appear in required to build a project. A Makefile automates the actual build itself.
The aim of this project is to develop a Graphic Processing Unit core targeting FPGA implementation.
basic debug tools while using FPGA boards