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Top Apps

  • Find out what (or who) is slowing down your network Find out what (or who) is slowing down your network Icon
    Find out what (or who) is slowing down your network Icon

    Get comprehensive network bandwidth analysis and performance monitoring with SolarWinds® Bandwidth Analyzer Pack.

    Network slow, but you don't know the cause? Use Bandwidth Analyzer Pack (BAP) to monitor and analyze network bandwidth performance and traffic patterns. With BAP, you can identify which users, applications, and protocols are consuming the most bandwidth. You can also monitor Wireless LAN Controller traffic to see what applications and clients are using your wireless network. Try it free for 30 days!
  • Infrastructure and application monitoring for Azure Infrastructure and application monitoring for Azure Icon
    Infrastructure and application monitoring for Azure Icon

    Monitor your Azure® infrastructure, application, and systems performance side by side in a single enterprise-monitoring tool

    So, you moved your applications and servers to Azure, but are they running any better and are you able to justify the investment? Without proper monitoring, you’re left guessing if application and server performance has improved, and when issues arise, you’re left scrambling to locate the root cause. SolarWinds® Server & Application Monitor (SAM) can monitor your Azure workloads side by side with your on-premises workloads to help ensure optimal application performance.
  • AIC-P1-ProcesadorSegmentado

    Práctica para la asignatura Arquitectura e Ingeniería de Computadores de 4º curso de Ingeniería Informática (Universidad de Extremadura). Simulación en VHDL de un procesador segmentado.

    Downloads: 0 This Week Last Update: See Project
  • Anie

    PID_control, real_time, matlab_simulink, xilinx_ise, fpga_spartan3e

    Embedded system design (VHDL description) based on Xilinx's Spartan3E Development Kit to perform real-time PID control and monitoring of time critical plants such as brushless DC motors, maglevs... vimeo.com/channels/anie prezi.com/gpbycavq499c/anie/

    Downloads: 0 This Week Last Update: See Project
  • Arcade Snake Game using verilog

    A arcade snake game purely written in verilog [ no asm or C ]

  • Blowfish VHDL Core

    BlowfishVHDL - free fully synthesizable Blowfish encryption algorithm hardware implementation.

    Downloads: 0 This Week Last Update: See Project
  • BlueSVEP Icon

    BlueSVEP

    Bluespec SystemVerilog Eclipse Plugin

    BlueSVEP is an Eclipse-based IDE for Bluespec SystemVerilog, a functional hardware description language based on a synthesizable subset of Haskell and SystemVerilog.

    Downloads: 0 This Week Last Update: See Project
  • Identify and respond to threats before damage is done Identify and respond to threats before damage is done Icon
    Identify and respond to threats before damage is done Icon

    A SIEM that makes it easy to use logs for security, compliance, and troubleshooting.

    SolarWinds® Log & Event Manager (LEM) delivers comprehensive Security Information and Event Management (SIEM) capabilities in a highly affordable, easy-to-use, and quick-to-deploy virtual appliance. LEM provides the visibility, security, and control that IT professionals need to alert on and respond to security threats, and assist in meeting the regulatory compliance guidelines of HIPAA, PCI DSS, SOX, and more. Try it free for 30 days!
  • FAZIA DAQ Icon

    FAZIA DAQ

    The aim of FAZIA project is to build a 4Pi array for charged particles

    The FAZIA project groups together more than 10 institutions in Nuclear Physics, which are working in the domain of heavy-ion induced reactions around and below the Fermi energy (10-100AMeV). The aim of the project is to build a 4Pi array for charged particles, with high granularity and good energy resolution, with A and Z identification capability over the widest possible range. It will use the up-to-date techniques concerning detection, signal processing and data flow, with full digital electronics. Neutron detection is also foreseen via the collaboration with the NEUTROMANIA group. FAZIA is designed to operate at stable and radioactive beams facilities like LNL-Legnaro, LNS-Catania in Italy, GANIL-SPIRAL and SPIRAL2 in France, GSI-FAIR in Germany in the horizon 2010-2015. The availability of the european radioactive beam facility EURISOL expected in the period 2015-2020 will also be a major opportunity for the FAZIA community.

    Downloads: 0 This Week Last Update: See Project
  • FREE_VHD_Lib

    A free VHDL IPs for general purpose FPGA developpement. Need GRLIB to work properly, to setup see README.

    Downloads: 0 This Week Last Update: See Project
  • FUI Audio DAC Icon

    FUI Audio DAC

    FPGA-Based USB-Input Audio Digital to Analogue Converter

    An open-hardware and -firmware project that implements a USB-input fully-digital class-D audio amplifier. All processing is done on FPGA, including the USB-physical, USB-SIE, HID interface, clock-recovery, bus voltage regulation, noise-shaping and PWM output. A Microchip PIC based remote control is also included. The remote maps to the media buttons of the USB HID interface. The volume control, next track, previous track, stop and play/pause functions are supported.

    Downloads: 0 This Week Last Update: See Project
  • GPS to Radio-controlled Clock Icon

    GPS to Radio-controlled Clock

    GPS to Radio-controlled Clock

    The purpose of this simple DIY project is to build an electronic circuit that received the GPS time signal, convert it to the radio-controlled clock format, and transmit that signal to the clock. Once built, there is no need for setup and maintenance, all you need is put this unit close to the window to receive GPS signal, and it will transmit the time signal to your radio-controlled clock.

  • Joint pictures image coder

    This is an image coder with fixed sampling, at a rate of up to 24 images per second (on XC2V1000-4 @ 40 MHz with res. up to 352x288).

    Downloads: 0 This Week Last Update: See Project
  • Focus on Business Growth with a VoIP Solution Focus on Business Growth with a VoIP Solution Icon
    Focus on Business Growth with a VoIP Solution Icon

    Cloud Phone Service. Built for Business.

    • Over 50 business-class features
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  • Notepad++ Verilog Plugin

    Verilog plugin for Notepad++

    Verilog processor for Notepad++. Current features: - Instantiate a module - Insert registers/wires from a module - Generate a test bench template - Automatically inserts a default header for a test bench - Insert a clocked always block v1.2.0 now supports ANSI and non-ANSI module declarations. To use this plugin, select the module declaration (including parameter and I/O definitions below for non-ANSI) and click SHIFT-CTRL-C. This selects the module and parses its components. After this, all other functions are available.

    Downloads: 108 This Week Last Update: See Project
  • Open HD Video Capture Card

    This card will capture High Definition Video 1280x720 at 30fps, and soon be capable of 60fps and maybe even 1080p. This is a hardware project so source code, RTL, and board CAD files will be involved. All IC's and parts should be easily available.

    Downloads: 0 This Week Last Update: See Project
  • OpenSOC86 Icon

    OpenSOC86

    Open implementation of the x86 architecture

    OpenSOC86 is an open implementation of the x86 architecture in Verilog. The current version only implements the 16-bit part (real mode). The processor is a pipelined architecture clocked at 100 MHz in a Cyclone II speed grade -6. Therefore it can be seen as similar to a 486 in real mode. Several peripherals are also implemented in a somewhat minimalistic way, but enough to be able to boot an IBM PCXT compatible bios and MSDOS 6.22. The current implementation is only proven to boot the bios and DOS in simulation. The system is targeted to run on the DE2-70 board. In order to run the system in hardware a SDRAM and SRAM controller need to be added. These are currently in development.

    Downloads: 1 This Week Last Update: See Project
  • OpenShader

    Open architecture GPU simulator and implementation

    Documentation, simulator, compiler, and Verilog implementation of a completely open-architecture graphics processing unit. This design is intended for academic and commercial purposes. The first step is to develop a detailed GPU simulator and compiler. The second step is to implement the GPU in synthesizable Verilog. The third step is to develop a feedback loop between the simulator and implementation, allowing power, performance, and reliability aspects of the hardware to feed back into ever more detailed and accurate simulations of a complete GPU. LICENSING Primary licensing is GPLv3. Secondary is Commercial. Commercial licensing (use incompatible with GPLv3) will be available via an elected or appointed non-profit Facilitator. Revenue will be invested per the discretion of the Facilitator and an advisory board. By contributing to this project, you agree to these terms. [See our Wiki for more information](https://sourceforge.net/p/openshader/wiki/)

  • PDP11 in FPGA

    Attempt to implement DEC PDP-11 minicomputer in Xilinx FPGA

    Downloads: 0 This Week Last Update: See Project
  • SASEBO Tools

    Toolkit to use the SASEBO GII boards more efficiently

    Documentation for the SASEBO GII boards is rather sparse and as we need to overcome a few hurdles to get our research project going, we want to share our experiences and make the generic tools available so that others can use it without having to redo all the work. What we're attempting to do is create a solution where one can use the USB bus to communicate with a Xilinx microblaze core on the target FPGA of the SASEBO board (via the control FPGA), use the onboard SRAM and develop coprocessors for the microblaze.

    Downloads: 0 This Week Last Update: See Project
  • Savanne

    This is my personal sourceforge file for personal projects that I intend to work on.

    Downloads: 0 This Week Last Update: See Project
  • VFBI - VHDL FBG Interrogation

    VHDL description of a FPGA-based FBG interrogation system

    VHDL that describes the digital circuits employed in a fiber Bragg grating interrogation system, currently implemented in a FPGA system.

    Downloads: 0 This Week Last Update: See Project
  • VHDL Notepad++ Plugin

    VHDL Plugin for the Notepad++ Editor

    VHDL plugin based on http://sourceforge.net/projects/nppvhdlplugin/ This version is enhanced to include: - Insert Instantiation - Insert Signals - Create Test Bench Framework - Insert Component - Make comments Doxygen compliant - Create New Behavioral/Structural Entity Template - Create New Package File Template - Insert Synchronous Process - Insert Asynchronous Process - Insert a Default Header The default header is set in the vhdlConfig.txt file.

    Downloads: 130 This Week Last Update: See Project
  • VHDT Icon

    VHDT

    VHDL Design Tool - code generation and project management

    Application simplifies the development and management of VHDL projects. The project is displayed in a well-arranged tree structure depending on the hierarchy of entities. It also helps to maintain projects in a consistent state. Other features include automatic generation of VHDL testbenches and structures based on user-defined templates. The NetBeans platform is used as a basis for the implementation.

    Downloads: 4 This Week Last Update: See Project
  • adms Icon

    adms

    ADMS is a code generator that converts electrical compact device models specified in high-level description language into ready-to-compile c code for the API of spice simulators. Repository migrated to: https://github.com/Qucs/ADMS For checkout do: git clone https://github.com/Qucs/ADMS.git

  • cMIPS Icon

    cMIPS

    cMIPS - an FPGA ready VHDL model for 5-stage pipeline, MIPS32r2 core

    This project was moved to https://gitlab.c3sl.ufpr.br/roberto/cmips The code here is no longer up to date. The VHDL model mimics the pipeline design described in Patterson & Hennessy's book (Computer Organisation and Design) and is an almost complete implementation of the MIPS32r2 instruction set. The TLB and assorted control registers will be included soon (as of fev 2015). The model was synthesized for an Altera EP4CE30F23. The model uses up 15% of combinational blocks and 5% logic registers.

    Downloads: 0 This Week Last Update: See Project
  • cccutils

    Clock and Control Card Utilities

    cccutils provide the sources of the CCC and the CCC-Fanout.

    Downloads: 0 This Week Last Update: See Project
  • giant

    GIAnT (Generic Implementation ANalysis Toolkit) is a platform for physical analysis of (embedded) devices. Primarily designed for hardware security analyses, it is built around an FPGA-based board for fault injection and side-channel analysis. This project has been supported by the German Federal Ministry of Education and Research BMBF (grant 01IS10026A, Project EXSET).

    Downloads: 0 This Week Last Update: See Project
  • lpACLib

    An Open-Source Library for Low-Power Approximate Computing Modules

    The “lpACLib” library contains the VHDL description of accurate and approximate versions of several arithmetic modules (like adders and multiplier of different bit-widths) and accelerators. Moreover, it also provides the corresponding software behavioral models/implementations developed in C and MATLAB to enable quality characterization. Besides our novel designs, it also contains implementations for several state-of-the-art arithmetic modules and their approximate versions. This open-source library facilitates research and development in approximate computing at higher abstraction levels, and to facilitate reproducible research and comparisons. In case of usage, please refer to our publication: Muhammad Shafique, Rehan Hafiz, Semeen Rehman, Walaa El-Harouni, Jörg Henkel, "Cross-Layer Approximate Computing: From Logic to Architectures", Design Automation Conference (DAC), 2016. Contributors: Authors, Vanshika Baoni, M. Abdullah Hanif http://ces.itec.kit.edu/lpACLib.php

    Downloads: 7 This Week Last Update: See Project
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