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System on Chip design generator.
SHELLEY Software HardwarE Light LanguagE Yep !
Spartan3A Starter Kit Oscilloscope with Java Client
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simple and practical RISC Processor work in Altera DE2 Board(made by TERASIC)
vcd2svg can parse Value Change Dump (VCD) files and draw an impulse diagram using Scalable Vector Graphics (SVG). It works together with the GHDL open-source simulator.
Common Lisp frontend to Verilog HDL -- use the Common Lisp macro system to generate reams of boring, ugly Verilog.
zuphinx (say zoo'finks) is an efficient VHDL design environment.
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