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  • Take Advantage of O365 + Online Backup Bundles Take Advantage of O365 + Online Backup Bundles Icon
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  • openSAFETY Demo Icon

    openSAFETY Demo

    An openSAFETY safe node demo application

    The openSAFETY Demo is an example implementation of an openSAFETY Safe Node (SN) with a simple GPIO application using POWERLINK as the underlying communication network. It is intended for people interested in openSAFETY and for evaluation purposes of openSAFETY. This demo only demonstrates the network capabilities and transport of openSAFEY frames. Additional software and hardware components are necessary to meet any necessary requirements demanded by notified bodies or related standards. The demo application consists of a part for handling the POWERLINK communication (POWERLINK Communication Processor, PCP), which is implemented on a FPGA platform and another part (application processor) executing the the user application, such as the openSAFETY stack and a sample application. ** The download of the openSAFETY Demo includes all sources and binaries for the FPGA part, as well as for the STMicro Nucleo-F401RE and Nucleo-F103RB development boards.**

    Downloads: 3 This Week Last Update: See Project
  • Synthesia synth platform

    Synthesia is an open hardware/software platform intended for creating standalone audio devices such as synthesizers on embedded processors.

    Downloads: 1 This Week Last Update: See Project
  • HDL-IP-Cores

    Platform for advanced open source IP-Core development, i. e. dynamic memory controllers for FPGAs.

    Downloads: 0 This Week Last Update: See Project
  • EduCPU

    Simple CPU for education

    This is a simple CPU design, written in Verilog, intended for educational purposes. The objective is to provide a simulatable processor where the source code exposes concepts in CPU microarchitecture.

    Downloads: 0 This Week Last Update: See Project
  • Vorbischip

    vorbis-hw is an open-source hardware implementation of an Ogg-Vorbis decoder. My current plan is to port the "tremor" codec to VHDL.

    Downloads: 0 This Week Last Update: See Project
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  • libVerilogVPI

    SEL for access verilog via PLI/VPI API. Tested with Icarus Verilog.

    SFENCE Extension Library (SEL) for access verilog function via PLI/VPI API to calls of standard SFENCE Function_Function objects.

    Downloads: 0 This Week Last Update: See Project
  • Inferno C++ to Verilog

    Convert C++ software programs into synthesisable Verilog using the Clang compiler frontend to parse and SystemC for intermediates.

    Downloads: 0 This Week Last Update: See Project
  • OpenWi

    Design and implementation of silicon and software for baseband processors conforming to IEEE wireless standards. Initial focus on WiMAX and WiFi.

    Downloads: 0 This Week Last Update: See Project
  • Napoleon Embedded SPARC V8

    Napoleon Embedded SPARC V8 32-bits

    The project aim to create a complete embedded SPARC V8 32 bits.

    Downloads: 0 This Week Last Update: See Project
  • Pulse Programmer Icon

    Pulse Programmer

    A programmable signal generator and RF synthesizer for scientific experiments, especially quantum computing and quantum information processing. It includes hardware, firmware, software, and documentation, all under an open source license.

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  • Verilog Design Checker

    Compiler-like program that checks Verilog source for common design errors. This tool can help beginning Verilog programmers who aren't aware of common design pitfalls and advanced Verilog programmers who want to double check large projects.

    Downloads: 1 This Week Last Update: See Project
  • verilog compiler

    A verilog language compiler written using Java and JavaCC. It produces a netlist, an ascii text file, of all the cell connections. It can compile very large circuits comprised of many modules.

    Downloads: 2 This Week Last Update: See Project
  • vaster

    Vaster is a EDA tool. It creates SystemC Cycle Accurate model from VerilogHDL RTL Model.

    Downloads: 0 This Week Last Update: See Project
  • GraphUIS

    Este proyecto presenta GraphUIS, una implementación de un periférico de video en un FPGA como un diseño modular caracterizado por no tener memoria dedicada. Se desarrolló como un proyecto académico en la Universidad Industrial de Santander.

  • pac-box (Portable Atari Control Box)

    A portable rebuilt of the Atari 2600 console. The target is to rebuild the hardware all inside a box which will be used as it's own control. The games will be stored into a Flash memory and a menu-driven TV interface, in a BIOS, will manage the options.

    Downloads: 0 This Week Last Update: See Project
  • BlueSVEP Icon

    BlueSVEP

    Bluespec SystemVerilog Eclipse Plugin

    BlueSVEP is an Eclipse-based IDE for Bluespec SystemVerilog, a functional hardware description language based on a synthesizable subset of Haskell and SystemVerilog.

    Downloads: 0 This Week Last Update: See Project
  • Humanoid, Robocup, Shanghai University

    The RoboCup Team of Shanghai University (aka. Strive Team) is now devoting itself to the Humanoid League Contest. Many features like machine vision, pace generation, speech cognition, etc. of the humanoid robots is rising here in the following years.

    Downloads: 0 This Week Last Update: See Project
  • Open RVC-CAL to HDL

    Open RVC-CAL to HDL (ORC2HDL) is an Eclipse Plugin which uses the Open RVC-CAL Compiler (ORCC) and the openForge HDL Synthesizer. This plugin gives the ability to generate HDL code from a RVC-CAL model.

    Downloads: 0 This Week Last Update: See Project
  • Oscillo

    This is a hardware/software simple USB Digital Storage Oscilloscope project.

    Downloads: 0 This Week Last Update: See Project
  • hardh264

    A hardware H.264 video encoder written in VHDL suited to non-interlaced IP cameras and megapixel cameras. Designed to be synthesized into an FPGA or ASIC. Fast and small. Modular. Extensible.

    Downloads: 0 This Week Last Update: See Project
  • openciphers

    This project is a collection of Open Source crypto cores and implementations relating to high speed cryptanalysis/cracking and complex implementations.

    Downloads: 0 This Week Last Update: See Project
  • X-RT

    X-RT: A portable multiprocessor real-time scheduling framework

    This project contains the material discussed in my PhD dissertation, entitled "Hardware/Software Design of Dynamic Real-Time Schedulers for Embedded Multiprocessor Systems." The source code is available in the SVN repository: https://sourceforge.net/p/xrt/code/6/tree/trunk/ and consists in two folders: 1) /X-RT : A portable multiprocessor scheduling framework supporting scheduling periodic real-time tasks according to the G-EDF (Global Earliest Deadline First) scheduling platform. Current version supports major POSIX systems (Linux, QNX). 2) Hardware_GEDF_Scheduler: is a hardware implementation in VHDL (targeting FPGAs) of the G-EDF multiprocessor scheduling policy.

    Downloads: 0 This Week Last Update: See Project
  • GalaxyIP

    Galaxy Intellectual Property Cores

    GalaxyIP (Galaxy Intellectual Property Cores) is a project devoted to accommodate a set of IP-Cores for embedded SoC development, based on the processor code named Voyager (StarTrek and the space probes).

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