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Top Apps

  • SolarWinds is #1 in network monitoring. SolarWinds is #1 in network monitoring. Icon
    SolarWinds is #1 in network monitoring. Icon

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  • Free tools and cores for FPGAs

    Tools for FPGA development and IP cores. This project provides tools, cores and documentation to develope FPGA applications. The project focuses on VHDL.

  • SmGen

    Verilog Finite State Machine (FSM) Code Generator

    SmGen is a finite state machine (FSM) generator for Verilog. On the other hand, it is not an FSM entry tool. The input is behavioral Verilog with clock boundaries specifically set by the designer. SmGen unrolls this behavioral code and generates an FSM from it in synthesizable Verilog. Clock boundaries are explicitly provided by the designer so there is good control on the expected timing

    Downloads: 0 This Week Last Update: See Project
  • PLP

    Powerfull pre-processor

    Powerful Verilog Preprocessor. PLP stands for Perl Pre-processor. Perl is used as "control language" that is embedded in the Verilog code (or any other code) to generate code on the fly. It is used commonly as a Verilog pre-processor but can be used with any target/output language (C, C++, Java, VHDL, plain text etc)

    Downloads: 3 This Week Last Update: See Project
  • sim-sim

    HDL Analyzer and Netlist Architect (HANA): An open source analysis and synthesis tool for design written in Verilog 2001 HDL

  • cincoportas

    Meus arquivos de mestrado

    Downloads: 0 This Week Last Update: See Project
  • CRM / Lead Management / Marketing Automation CRM / Lead Management / Marketing Automation Icon
    CRM / Lead Management / Marketing Automation Icon

    More than just software – it’s a solution customized specifically for your business. We strive to give customers exactly what they want.

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  • DSPSource

    Simple signal processing projects in Scilab and Matlab

    Downloads: 0 This Week Last Update: See Project
  • Verilog Perl

    The Verilog-Perl distribution provides Perl preprocessing, parsing and utilities for the Verilog Language. It is also available from CPAN under the Verilog:: namespace.

    Downloads: 0 This Week Last Update: See Project
  • openciphers

    This project is a collection of Open Source crypto cores and implementations relating to high speed cryptanalysis/cracking and complex implementations.

    Downloads: 0 This Week Last Update: See Project
  • zuphinx

    zuphinx (say zoo'finks) is an efficient VHDL design environment.

    Downloads: 0 This Week Last Update: See Project
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