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Simple signal processing projects in Scilab and Matlab
Tools for FPGA development and IP cores. This project provides tools, cores and documentation to develope FPGA applications. The project focuses on VHDL.27 weekly downloads
Powerfull pre-processor2 weekly downloads
Verilog Finite State Machine (FSM) Code Generator1 weekly downloads
The Verilog-Perl distribution provides Perl preprocessing, parsing and utilities for the Verilog Language. It is also available from CPAN under the Verilog:: namespace.
Meus arquivos de mestrado
This project is a collection of Open Source crypto cores and implementations relating to high speed cryptanalysis/cracking and complex implementations.
HDL Analyzer and Netlist Architect (HANA): An open source analysis and synthesis tool for design written in Verilog 2001 HDL3 weekly downloads
zuphinx (say zoo'finks) is an efficient VHDL design environment.