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- Programming Language: VHDL/Verilog ×
This is the award-winning FALCON I object recognition system! Capable of tracking up to 12 different objects simultaneously, and with over 6 times the raw resolution of the CMUCam, this is one of the most powerful vision systems in its class.1 weekly downloads
This project aim to develop a suite of tool to ease the development of ASIC/FPGA solution. The final program should be an IDE enabling the creation and specification of a project from it's start to finish.
Susara is a development architecture for software-defined radio (SDR) applications. It assists developers to focus on the high-level design of radio components, from which efficient platform-specific source code is automatically generated.
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The aim is to develop a foundation for a FPGA hardware platform able to run Linux kernel and software. It must be easy to add hardware accelerated ip-cores to the FPGA. Ethernet and TCP/IP is a corner stone of the hardware and software.
A Verilog design for a simple ASIC that executes the Ray Tracing Algorithm.1 weekly downloads
Digital waveform viewer/editor. eWave is a visual waveform timing editor compatible with VCD format (with image export possibilities) intended to be used in educational or technological (digital design) purposes. It is distributed as an Eclipse plugin.
A hardware H.264 video encoder written in VHDL suited to non-interlaced IP cameras and megapixel cameras. Designed to be synthesized into an FPGA or ASIC. Fast and small. Modular. Extensible.
Please see https://sourceforge.net/projects/smpla/?source=directory
Este proyecto es una iniciativa para reconstruir la plataforma PUMA MA2000 de la empresa TeQuipment ltd. por medio de la implementación de un sistema empotrado basado en tecnología FPGA.
mov86 is a free soft-core processor written in VHDL. The aim of the project is to develop a CPU-core with maximum compatibility to intel x86 architecture.
In this project a simple WAV player will be implemented using an FPGA. The WAV player is able to play music which is digitally stored in a semiconductor memory device. Check out from trunk or use the taged version from download.
This is an image coder with fixed sampling, at a rate of up to 24 images per second (on XC2V1000-4 @ 40 MHz with res. up to 352x288).3 weekly downloads
An arbitrary waveform generator (AWG) is a piece of electronic test equipment used to generate any arbitrarily defined electrical waveform as it's output. This waveforms can be generated with MATLAB.
Scicos-HDL is a tool to design digital circuit system; it integrates the hardware circuit, algorithm and Scilab/Scicos environment as a plat for digital circuit design, simulation and Hardware Description Language generation. ZhangDong & KangCai
Synthesia is an open hardware/software platform intended for creating standalone audio devices such as synthesizers on embedded processors.
This project aims to generate video signal using an FPGA development board
The Verilog-Perl distribution provides Perl preprocessing, parsing and utilities for the Verilog Language. It is also available from CPAN under the Verilog:: namespace.
In this project we have developed a navigation tool for visually impaired person by which they can move to different locations in their surrounding without the help of others.
Embedded Co-Design @ University of West of England Members: Matthew Browne
CRC Generator is a command-line application that generates Verilog or VHDL code for CRC of any data width between 1 and 1024 and polynomial width between 1 and 1024. The code is written in C for Win32, bus easily portable for other platforms5 weekly downloads
Palette for computer architecture design
Parallelsimu provides interfaces for parallel simulation of RTL descriptions of complex hardware designs(SoCs, CPUs and etc.) written in Verilog HDL.
1chipMSX Unofficial Firmware Pack
This is a fork of the Elphel cameras firmware CVS, fully open to contributions from the elphel users and developers community Everyone can submit patches or obtain CVS access for this fork Stable changes will be ported to the main CVS upon approv
Approach to design a digital FM receiver using a FPGA as main unit