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- Programming Language: VHDL/Verilog ×
vcd2svg can parse Value Change Dump (VCD) files and draw an impulse diagram using Scalable Vector Graphics (SVG). It works together with the GHDL open-source simulator.
Collection of VHDL libraries for ASIC/FGPA development
Simple AVR OS7 weekly downloads
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PID_control, real_time, matlab_simulink, xilinx_ise, fpga_spartan3e1 weekly downloads
The ixo.de USB JTAG pod and firmware allows to access JTAG-capable chips via USB and a protocol like Altera USB-Blaster.
Genode FX is a composition of hardware and software components that enable the creation of fully fledged graphical user interfaces as system-on-chip solutions using commodity FPGAs such as Xilinx' Spartan3 and Virtex FPGAs.4 weekly downloads
Yet Another DLX based Architecture System On a Chip (YADASOC) is a RTL Verilog implenetation of a DLX based CPU and subsystems.
The project uses the infrared camera from the wiimote to track hand gestures. This tracking is performed on an Altera DE2-70 FPGA
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Oscilloscope components, including 100MHz quad A/D, VHDL code for Xilinx FPGA, and driver for Octave or Matlab.3 weekly downloads
Academic project of USB controller
simple and practical RISC Processor work in Altera DE2 Board(made by TERASIC)
Spartan3A Starter Kit Oscilloscope with Java Client
SHELLEY Software HardwarE Light LanguagE Yep !
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A VHDL - Verilog SAD256 module
Open RVC-CAL to HDL (ORC2HDL) is an Eclipse Plugin which uses the Open RVC-CAL Compiler (ORCC) and the openForge HDL Synthesizer. This plugin gives the ability to generate HDL code from a RVC-CAL model.
Picode is the ultimate VHDL picode 16 to 32 bits controller. It is described in only one entity and is implementable in standard FPGAs. It has it own compiler. Picode is designed to take only one or two clock cycle duration per instruction.
Attempt to implement DEC PDP-11 minicomputer in Xilinx FPGA
This is a hardware/software simple USB Digital Storage Oscilloscope project.
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A hardware project to interface a microcontroller (currently PIC family) to a LED driver consisting of a CPLD to drive an LED array with 35 LEDs... The source codes (c/vhdl) and schematics are going to be freely available
A command-line application that generates Verilog or VHDL code for an LFSR counter of any value up to 63 bit wide. The code is written in C for Win32 platform1 weekly downloads
vhdl para curso embebidos jaquenod
The HDL Complexity Tool parses large complex hardware projects' source code to produce useful complexity results. GOALS: 1)Practical, effective and simple 2) Integrates with existing design flows 3) Used on real projects 4) Based on existing research1 weekly downloads
This project includes a set of tools and guidelines designed for rapid production of large-scale embedded systems projects. The tools enable quick generation of reusable, reconfigurable hardware, using a user-specified hardware description language.
The aim of this project is to develop a Graphic Processing Unit core targeting FPGA implementation.
FreeCores is a project to provide and foster a place for the sharing and development of hardware designs, in the spirit of freedom, starting with all the Free Hardware cores moved from OpenCores.org, and indexed at FreeCores.org.