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- Programming Language: VHDL/Verilog ×
Compiler-like program that checks Verilog source for common design errors. This tool can help beginning Verilog programmers who aren't aware of common design pitfalls and advanced Verilog programmers who want to double check large projects.
The VHDL Lookup Table Generator generates a table in vhdl from a C++-table. I was too lazy to write a parser. Code is found in the CVS (scroll down for url): http://vhdl-lut-gen.cvs.sourceforge.net/*checkout*/vhdl-lut-gen/vhdl-lut-gen/vhdl-lut-gen.cpp
Implementação de um serviço de otimização de funções baseado em Algorítmos Genéticos em um Hardware dedicado e disponível para utilização através de uma interface Web
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Implementation of Motorola microprocessor MC68000 in FPGA
A Decimal Counter written in VHDL controlled by some buttons.
a micro processor 16 bits optimized to hold in a CPLD
Holds all information related to creating an Agile Development Methodology geared towards ASIC/FPGA Verification.
A verilog language compiler written using Java and JavaCC. It produces a netlist, an ascii text file, of all the cell connections. It can compile very large circuits comprised of many modules.1 weekly downloads
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Wireless Sensor Node sniffer hardware front-end and GUI
Vaster is a EDA tool. It creates SystemC Cycle Accurate model from VerilogHDL RTL Model.
Este proyecto presenta GraphUIS, una implementación de un periférico de video en un FPGA como un diseño modular caracterizado por no tener memoria dedicada. Se desarrolló como un proyecto académico en la Universidad Industrial de Santander.
The main target of this project is to create a Open Source System on Chip generator for FPGA. This generator will use following technologies: Python, Wishbone SoC bus specifications and VHDL.
Oscilloscope set top box for PC. There are many projects like that, but we want to try to design it in our way.
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Common Lisp frontend to Verilog HDL -- use the Common Lisp macro system to generate reams of boring, ugly Verilog.
Project that converts the Gameboy advance into a oscilloscope with a frequency range of 0-50MHZ
Framework for Adaptive Hardware Concurrent Systems with DPR-FPGAs
Provides a simple way to interact with icarus verilog tool.
This is a simple DES algorithm implemented in FPGA platform. Mainly this system was written by C and interpreted into VHDL.
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Inane's not a NES emulator. It is a reimplementation of the original NES hardware in VHDL with the goal of making it fully synthesize in hardware.
The system allows running and controlling the MAC controller on the Xilinx board with Virtex. This way the project provides a set of features and functionality to easy build the application and eCos and TCP/IP FreeBSD with access to Xilinx MAC controller1 weekly downloads
Its a VHDL plugin for Notepad++ which is simular with the one which is available on emacs (Copy a selcted entity port and then paste it as instatiation , Signals or as Testbench )6 weekly downloads
Simple signal processing projects in Scilab and Matlab
A portable rebuilt of the Atari 2600 console. The target is to rebuild the hardware all inside a box which will be used as it's own control. The games will be stored into a Flash memory and a menu-driven TV interface, in a BIOS, will manage the options.
Plugin Eclipse/VDT supports hardware development in VHDL/Verilog, allowing to easily integrate command-line controlled tools in Eclipse. Underlying Eclipse/ExDT plugin provides integration means that may be used for other languages and applications.
SImple Oscilloscope based on FPGA. 1,2,4 channels, 100~250Msps per channel. Channels can be pipelined to 400Msps~1Gsps or working separately. DVI or LVDS output directly to an LCD monitor or panel. No frame buffer needed. low cost.