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- Programming Language: VHDL/Verilog ×
Ospu is a soft processor for FPGA.
A Development Framework for Coldfire
CoreTML framework is an open-source template-based configuration system allowing the developer to create parametrized templates by inserting special content to any text files. Its main purpose is to serve as a toolkit for semiconductor IP core creation (based on VHDL/Verilog).
ThousandEyes extends visibility across corporate networks as well as the public Internet, helping to solve issues from the branch through MPLS links and SIP trunks to service provider networks. Simulate pre-deployment capacity, monitor detailed performance metrics and see how QoS settings impact call quality.Sponsored Listing
VHDL description of a FPGA-based FBG interrogation system
SEL for access verilog via PLI/VPI API. Tested with Icarus Verilog.
This project is an Adaptive LMS Equalizer / Filter implementation with piplined architecture for speedier performance.This project implements equalizer in VHDL so can be used with FPGA/CPLD
Expansion card for 8 bit computer Sharp MZ-800. Connection to SD / MMC card with FAT16 filesystem. Emulated FD controller. MZF repository. This project is already stoped. Please see the MZ800 Unicard 2nd generation https://sourceforge.net/projects/mz800ukp1/
A methodology to create netlists for printed circuit board layout using a novel PCB specific HDL as the source language.
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we want create a prccessor for neuralcomputers .
Convert C++ software programs into synthesisable Verilog using the Clang compiler frontend to parse and SystemC for intermediates.
the goal of this project is to build a stack for Lonworks Protocol and device working on this protocol
Custom Architecture Generator Tool is a software based on the Netbeans Platform, the main purpose is to accelerate the embedded system realisation with a high level description: VHDL code,C2VHDL conversion,Quartus project generation,real time application
This project aims to collect generic arithmetic modules described in VHDL into one library for further reuse.
Icarus Verilog is an open source Verilog compiler that supports the IEEE-1364 Verilog HDL including IEEE1364-2005 plus extensions.125 weekly downloads
Design and implementation of silicon and software for baseband processors conforming to IEEE wireless standards. Initial focus on WiMAX and WiFi.
The goal of this project is to develop an easily modifiable combination of VHDL firmware and LabView drivers for use with laboratory automation control and data acquisition using Terasic's DE2 board and the ISP1362 USB interface chip.
HDL Analyzer and Netlist Architect (HANA): An open source analysis and synthesis tool for design written in Verilog 2001 HDL2 weekly downloads
VeriWell is a full Verilog simulator. It supports nearly all of the IEEE1364-1995 standard, as well as PLI 1.0. Yes, VeriWell *is* the same simulator that was sold by Wellspring Solutions in the mid-1990 and was included with the Thomas and Moorby book70 weekly downloads
FSMDesigner is a C++ based implementation for a Finite State Machine (FSM) design tool with integrated Hardware Description Language (HDL) generation. FSMDesigner4 uses the Simple-Moore FSM model guaranteeing efficient fast complex control circuits.7 weekly downloads
We are currently working with professors Bruce Land and Paul Kintner to develop a hardware mobile GPS receiver on an FPGA, capable of receiving L1 civilian GPS signals in real time.
The H.264 VHDL core is a hardware implementation of the H.264 video compression algorithm. The core accepts up to the highest resolution HDTV video stream as input and outputs the encoded bitstream. Simple, fully synchronous design with low gate count.
A arcade snake game purely written in verilog [ no asm or C ]1 weekly downloads
This project includes 2 parts: the open FPGA+DSP architecture for the GPS hardware and the GPS software running in embedded system and PC
Oscilloscope using a VGA monitor and a cpld