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- Programming Language: VHDL/Verilog ×
This project is the video controller of commodore 64 embedded in FPGA12 weekly downloads
Tool to convert matlab coding to xilinx execution format
GIAnT (Generic Implementation ANalysis Toolkit) is a platform for physical analysis of (embedded) devices. Primarily designed for hardware security analyses, it is built around an FPGA-based board for fault injection and side-channel analysis. This project has been supported by the German Federal Ministry of Education and Research BMBF (grant 01IS10026A, Project EXSET).2 weekly downloads
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Open RVC-CAL to HDL (ORC2HDL) is an Eclipse Plugin which uses the Open RVC-CAL Compiler (ORCC) and the openForge HDL Synthesizer. This plugin gives the ability to generate HDL code from a RVC-CAL model.
Please see https://sourceforge.net/projects/smpla/?source=directory
The foosball game is implemented in VHDL for use with the Altera DE2 FPGA board with the visual interface in a VGA monitor and input interface in a PS/2 keyboard.1 weekly downloads
In this project a simple WAV player will be implemented using an FPGA. The WAV player is able to play music which is digitally stored in a semiconductor memory device. Check out from trunk or use the taged version from download.
A free VHDL IPs for general purpose FPGA developpement. Need GRLIB to work properly, to setup see README.
CoreTML framework is an open-source template-based configuration system allowing the developer to create parametrized templates by inserting special content to any text files. Its main purpose is to serve as a toolkit for semiconductor IP core creation (based on VHDL/Verilog).
We are currently working with professors Bruce Land and Paul Kintner to develop a hardware mobile GPS receiver on an FPGA, capable of receiving L1 civilian GPS signals in real time.
xswifs stands for: cross SoftWare Interfaces. This project provide examples (snippets) for interfacing various software tools and languages with various mechanism. It has been created to help in HW/SW co-simulation and to provide benchmarks.
This project aim to develop a suite of tool to ease the development of ASIC/FPGA solution. The final program should be an IDE enabling the creation and specification of a project from it's start to finish.
PID_control, real_time, matlab_simulink, xilinx_ise, fpga_spartan3e1 weekly downloads
This is a collection of tools and a code library to assist engineers who are developing SystemVerilog based verification environments. Components include utility libraries, scoreboard and shutdown manager implementation, register tool, etc.
Cell Matrix Model Simulator
A command-line application that generates Verilog or VHDL code for an LFSR counter of any value up to 63 bit wide. The code is written in C for Win32 platform1 weekly downloads
CRC Generator is a command-line application that generates Verilog or VHDL code for CRC of any data width between 1 and 1024 and polynomial width between 1 and 1024. The code is written in C for Win32, bus easily portable for other platforms4 weekly downloads
Writing Testbenches for FPGA/ASIC design is always a very fastidious and boring task. This project helps any FPGA/ASIC designer by providing a full RTL test environment with C support.
The ixo.de USB JTAG pod and firmware allows to access JTAG-capable chips via USB and a protocol like Altera USB-Blaster.
An implementation of neural graphs
Frupo stands for Frugal Processor. The idea is to create a small footprint,implementation independent,soft core optimized for easy C programming. The project involves creation of the core itself as well as a toolchain to support it.
The aim of FAZIA project is to build a 4Pi array for charged particles
Asynchronous Spatial Division Multiplexing Router for On-Chip Networks
SystemVerilog module to substitute Verilog PLA system tasks.