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- Programming Language: VHDL/Verilog ×
mov86 is a free soft-core processor written in VHDL. The aim of the project is to develop a CPU-core with maximum compatibility to intel x86 architecture.
Open Source Hardware For Industrial Automation
Open-source alternative partial reconfiguration flow for Xilinx FPGAs1 weekly downloads
An openSAFETY safe node demo application27 weekly downloads
This project is a collection of Open Source crypto cores and implementations relating to high speed cryptanalysis/cracking and complex implementations.
A portable rebuilt of the Atari 2600 console. The target is to rebuild the hardware all inside a box which will be used as it's own control. The games will be stored into a Flash memory and a menu-driven TV interface, in a BIOS, will manage the options.
Picode is the ultimate VHDL picode 16 to 32 bits controller. It is described in only one entity and is implementable in standard FPGAs. It has it own compiler. Picode is designed to take only one or two clock cycle duration per instruction.
Python Hardware Processor1 weekly downloads
System on Chip design generator.
Scicos-HDL is a tool to design digital circuit system; it integrates the hardware circuit, algorithm and Scilab/Scicos environment as a plat for digital circuit design, simulation and Hardware Description Language generation. ZhangDong & KangCai2 weekly downloads
SHELLEY Software HardwarE Light LanguagE Yep !
HDL Analyzer and Netlist Architect (HANA): An open source analysis and synthesis tool for design written in Verilog 2001 HDL16 weekly downloads
SImple Oscilloscope based on FPGA. 1,2,4 channels, 100~250Msps per channel. Channels can be pipelined to 400Msps~1Gsps or working separately. DVI or LVDS output directly to an LCD monitor or panel. No frame buffer needed. low cost.
Spartan3A Starter Kit Oscilloscope with Java Client1 weekly downloads
Please see https://sourceforge.net/projects/smpla/?source=directory1 weekly downloads
SystemVerilog module to substitute Verilog PLA system tasks.6 weekly downloads
CPLD clone of the ZX-Spectrum 48K
simple and practical RISC Processor work in Altera DE2 Board(made by TERASIC)
In this project we have developed a navigation tool for visually impaired person by which they can move to different locations in their surrounding without the help of others.
Vaster is a EDA tool. It creates SystemC Cycle Accurate model from VerilogHDL RTL Model.
vcd2svg can parse Value Change Dump (VCD) files and draw an impulse diagram using Scalable Vector Graphics (SVG). It works together with the GHDL open-source simulator.
Common Lisp frontend to Verilog HDL -- use the Common Lisp macro system to generate reams of boring, ugly Verilog.
A verilog language compiler written using Java and JavaCC. It produces a netlist, an ascii text file, of all the cell connections. It can compile very large circuits comprised of many modules.1 weekly downloads
Its a VHDL plugin for Notepad++ which is simular with the one which is available on emacs (Copy a selcted entity port and then paste it as instatiation , Signals or as Testbench )13 weekly downloads