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- Programming Language: VHDL/Verilog ×
VSYML is an automated symbolic simulator for VHDL designs.
Writing Testbenches for FPGA/ASIC design is always a very fastidious and boring task. This project helps any FPGA/ASIC designer by providing a full RTL test environment with C support.
In this project a simple WAV player will be implemented using an FPGA. The WAV player is able to play music which is digitally stored in a semiconductor memory device. Check out from trunk or use the taged version from download.
VHDL Design Tool - code generation and project management5 weekly downloads
This project is the video controller of commodore 64 embedded in FPGA
Devellopement d'un controlleur d'affichage (VIC) du commodore 64 embarqué dans un FPGA avec controlleur d'animation integré.
Tool-independent Makefile generator for VHDL models.
vcomp is a verilog compiler for x86 linux targets - it was a commercial product which is now in the process of being GPL'd
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VeriWell is a full Verilog simulator. It supports nearly all of the IEEE1364-1995 standard, as well as PLI 1.0. Yes, VeriWell *is* the same simulator that was sold by Wellspring Solutions in the mid-1990 and was included with the Thomas and Moorby book21 weekly downloads
Compiler-like program that checks Verilog source for common design errors. This tool can help beginning Verilog programmers who aren't aware of common design pitfalls and advanced Verilog programmers who want to double check large projects.
The Verilog-Perl distribution provides Perl preprocessing, parsing and utilities for the Verilog Language. It is also available from CPAN under the Verilog:: namespace.
vrq is verilog parser that supports plugin tools to process verilog. Current plugins include tools to perform x-propagation and to auto build hiearchy.
This project aims to generate video signal using an FPGA development board
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ASIC research and development
Tools and libraries for use with systemc and verilog
vorbis-hw is an open-source hardware implementation of an Ogg-Vorbis decoder. My current plan is to port the "tremor" codec to VHDL.
Firmware development/ improvement for the digital storage oscilloscope "Welec 2000a- series".67 weekly downloads
The project uses the infrared camera from the wiimote to track hand gestures. This tracking is performed on an Altera DE2-70 FPGA
X-RT: A portable multiprocessor real-time scheduling framework
An FPGA based system, using captured video as source of a basketball movement. Human movement is detected and translated into motion vectors to hit a virtual ball.
Yet Another DLX based Architecture System On a Chip (YADASOC) is a RTL Verilog implenetation of a DLX based CPU and subsystems.
This library supports interoperability between components written for different verification methodologies such as VMM and OVM. This is maintained by the Accellera Verification Intellectual Property Technical Subcommittee.1 weekly downloads
ADMS is a code generator that converts electrical compact device models specified in high-level description language into ready-to-compile c code for the API of spice simulators. Repository migrated to: https://github.com/Qucs/ADMS For checkout do: git clone https://github.com/Qucs/ADMS.git131 weekly downloads
FFT co-processor in Verilog based on the KISS FFT8 weekly downloads
cMIPS - an FPGA ready VHDL model for 5-stage pipeline, MIPS32r2 core