Project SUZAKU, home of software development based on SUZAKU FPGA board
A VHDL - Verilog SAD256 module
This is my personal sourceforge file for personal projects that I intend to work on.
What would verilog code translated to unlambda look like? This question has puzzled me for a long time and I've decided to do a unlambda backend to my c->verilog compiler. Come to think of it, why stop at unlambda? I will go all the way to NAND gates.
Scicos-HDL is a tool to design digital circuit system; it integrates the hardware circuit, algorithm and Scilab/Scicos environment as a plat for digital circuit design, simulation and Hardware Description Language generation.
Simple RISC microprocessor development project
Verilog Finite State Machine (FSM) Code Generator
SmGen is a finite state machine (FSM) generator for Verilog. On the other hand, it is not an FSM entry tool. The input is behavioral Verilog with clock boundaries specifically set by the designer. SmGen unrolls this behavioral code and generates an FSM from it in synthesizable Verilog. Clock boundaries are explicitly provided by the designer so there is good control on the expected timing
Susara is a development architecture for software-defined radio (SDR) applications. It assists developers to focus on the high-level design of radio components, from which efficient platform-specific source code is automatically generated.
Synthesia is an open hardware/software platform intended for creating standalone audio devices such as synthesizers on embedded processors.
HW(VHDL) and SW of logic analyzer and On-Chip-Verification(OCV) for Value Change Dump(VCD) file format that exported to seemd SystemC ,ModelSIM, and many other EDA tools. Very easy and Simple.
This is a collection of tools and a code library to assist engineers who are developing SystemVerilog based verification environments. Components include utility libraries, scoreboard and shutdown manager implementation, register tool, etc.
Make your own virtual FPGA system and profile deeply with CI.
TestDrive Profiling Master is a free simulation software for Verilog/SystemVerilog and C/C++. It supports a CI (Continuous Integration) activity for H/W & S/W engineers' cooperation. Run by MS Windows environment, its use is governed by MIT License(Profiles) and LGPLv3(TestDrive Profiling Master). Based on the powerful compiler Verilator and GCC, TestDrive Profiling Master provides a totally free virtual FPGA system environment with various dynamic documents for profiling in deep on your system design. It performs a seamless conversion to a real FPGA environment without any changes of your testing software. I hope you will accomplish a successful design with TestDrive Profiling Master. Q&A : firstname.lastname@example.org
The HDL Complexity Tool parses large complex hardware projects' source code to produce useful complexity results. GOALS: 1)Practical, effective and simple 2) Integrates with existing design flows 3) Used on real projects 4) Based on existing research
The SBus is a family of high-speed packet-based databus standards, suitable for both networking and interdevice communication. They are optimized for high data density transactions. This project creates and documents the standards, schematics, and driver
The goal of this project is to develop an easily modifiable combination of VHDL firmware and LabView drivers for use with laboratory automation control and data acquisition using Terasic's DE2 board and the ISP1362 USB interface chip.
Academic project of USB controller
VHDL description of a FPGA-based FBG interrogation system
VHDL that describes the digital circuits employed in a fiber Bragg grating interrogation system, currently implemented in a FPGA system.
Oscilloscope using a VGA monitor and a cpld
VHDL FSM Generator, like the name says, is an application that will allow you to easily generate a finite state machine in VHDL without any (or very little) VHDL knowledge. The source code was programmed in Delphi 7.
The VHDL Lookup Table Generator generates a table in vhdl from a C++-table. I was too lazy to write a parser. Code is found in the CVS (scroll down for url): http://vhdl-lut-gen.cvs.sourceforge.net/*checkout*/vhdl-lut-gen/vhdl-lut-gen/vhdl-lut-gen.cpp
VHDL Plugin for the Notepad++ Editor
VHDL plugin based on http://sourceforge.net/projects/nppvhdlplugin/ This version is enhanced to include: - Insert Instantiation - Insert Signals - Create Test Bench Framework - Insert Component - Make comments Doxygen compliant - Create New Behavioral/Structural Entity Template - Create New Package File Template - Insert Synchronous Process - Insert Asynchronous Process - Insert a Default Header The default header is set in the vhdlConfig.txt file.
Application defines templates of VHDL structures, which allows us comfortly generate most used VHDL structures. It can also work with VHDL testbench templates from which can be created VHDL testbenches of existing projects.
VSYML is an automated symbolic simulator for VHDL designs.
Writing Testbenches for FPGA/ASIC design is always a very fastidious and boring task. This project helps any FPGA/ASIC designer by providing a full RTL test environment with C support.
In this project a simple WAV player will be implemented using an FPGA. The WAV player is able to play music which is digitally stored in a semiconductor memory device. Check out from trunk or use the taged version from download.