Open architecture GPU simulator and implementation
Documentation, simulator, compiler, and Verilog implementation of a completely open-architecture graphics processing unit. This design is intended for academic and commercial purposes. The first step is to develop a detailed GPU simulator and compiler. The second step is to implement the GPU in synthesizable Verilog. The third step is to develop a feedback loop between the simulator and implementation, allowing power, performance, and reliability aspects of the hardware to feed back into ever more detailed and accurate simulations of a complete GPU. LICENSING Primary licensing is GPLv3. Secondary is Commercial. Commercial licensing (use incompatible with GPLv3) will be available via an elected or appointed non-profit Facilitator. Revenue will be invested per the discretion of the Facilitator and an advisory board. By contributing to this project, you agree to these terms. [See our Wiki for more information](https://sourceforge.net/p/openshader/wiki/)
A software package that will combine different embedded computing platforms with home exercise equipment and a Qt client program in order to provide tracking of health and exercise performance.
Design and implementation of silicon and software for baseband processors conforming to IEEE wireless standards. Initial focus on WiMAX and WiFi.
The main target of this project is to create a Open Source System on Chip generator for FPGA. This generator will use following technologies: Python, Wishbone SoC bus specifications and VHDL.
This is a hardware/software simple USB Digital Storage Oscilloscope project.
Ospu is a soft processor for FPGA.
A methodology to create netlists for printed circuit board layout using a novel PCB specific HDL as the source language.
Attempt to implement DEC PDP-11 minicomputer in Xilinx FPGA
Programmable Electronic Controller
Programmable Electronic Controller for advanced instrumentation.
Powerful Verilog Preprocessor. PLP stands for Perl Pre-processor. Perl is used as "control language" that is embedded in the Verilog code (or any other code) to generate code on the fly. It is used commonly as a Verilog pre-processor but can be used with any target/output language (C, C++, Java, VHDL, plain text etc)
Code and documentation for the PSU Mars Society Rover
PVSim is a Portable Verilog Simulator for Mac OSX, Linux, and Windows. It features a fast compile-simulate-display cycle. The core is in C++, and the GUI, wxPython.
Palette for computer architecture design
Palette for computer architecture design
Parallelsimu provides interfaces for parallel simulation of RTL descriptions of complex hardware designs(SoCs, CPUs and etc.) written in Verilog HDL.
Framework for Adaptive Hardware Concurrent Systems with DPR-FPGAs
This project introduces new FPGA architectural tools and Linux OS modifications that aid in supporting Dynamic Partial Reconfiguration (DPR) on FPGAs for concurrent control. It shows that control systems benefit from hardware concurrency, meaning that by moving the control intelligence into hardware, the negative effects inherent to threads and their scheduler are minimized. This leaves software with the role of a high-level administrator rather than an executor, thereby eliminating unnecessary bottlenecks. The tools described in this project enable the hardware engineer to develop DPR-FPGA systems more effectively for rapid control system development. For more information, related papers and user guide, please refer to: - https://sourceforge.net/p/prhardware/wiki/Home/ - http://www2.ensc.sfu.ca/research/iDEA/personel/victor_lesau.htm
Electronic design and programming tools suite like Eagle, MpLab
Currently Only MacOS is Present, PreAlpha means not Ready to use, Application is provided Without Strict Garantee, License not OSI. All others platform Windows, Linux, HaikuOS STILL under TEST, Dummy "Hello world" is provided instead Project2306 IDE : Application pour la programmation de Microcontroleurs et d' Application Electronique Project2306 IDE : for All whom want to Create and Develop on Embed Platform Software as Programming Tools suite and PCB Design Planned Features : Similar with mainstream market tools IDE and GUI Wrapper like : LabView©, Proteus©, MPLab©, Eagle CAD©, Tools Suite for Most Market Microcontroller. Tools suite for Arduino, Pinguino, Pic, AVR, ARM, Basic Stamp, Risc, other platform Fully Integrated IDE. Adobe PDF Help section SQL Connectivity Community Avail : https://www.facebook.com/Project-Core-2306-Nextgen-Eda-pcbradide-for-Mcumacoslinuxwindows-138250749681138/?fref=ts
A simple processor which has an 8-bit data bus and a 13 bit address bus. The memory is 8192 x 8, instructions are 8 or 16 bits wide, and all opcodes are 3 or 4 bits wide.
A programmable signal generator and RF synthesizer for scientific experiments, especially quantum computing and quantum information processing. It includes hardware, firmware, software, and documentation, all under an open source license.
Ray Tracing micro-processor RTMP. Features: * Programmable pixel shaders. * SIMD 32-bit ALU. * Hardware support for Octree scene traversal. * Ray intersection cache. * Support for mutiple instances of RTMP working concurrently.
A Verilog design for a simple ASIC that executes the Ray Tracing Algorithm.
Este proyecto es una iniciativa para reconstruir la plataforma PUMA MA2000 de la empresa TeQuipment ltd. por medio de la implementación de un sistema empotrado basado en tecnología FPGA.
Collection of VHDL libraries for ASIC/FGPA development
Robert 2 is a robot, but doesn't exist yet. This project intend to develop all the software to build it
SAP1 is a small didactic processor created by professor Malvino.
Toolkit to use the SASEBO GII boards more efficiently
Documentation for the SASEBO GII boards is rather sparse and as we need to overcome a few hurdles to get our research project going, we want to share our experiences and make the generic tools available so that others can use it without having to redo all the work. What we're attempting to do is create a solution where one can use the USB bus to communicate with a Xilinx microblaze core on the target FPGA of the SASEBO board (via the control FPGA), use the onboard SRAM and develop coprocessors for the microblaze.