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- Programming Language: VHDL/Verilog ×
FSMDesigner is a C++ based implementation for a Finite State Machine (FSM) design tool with integrated Hardware Description Language (HDL) generation. FSMDesigner4 uses the Simple-Moore FSM model guaranteeing efficient fast complex control circuits.3 weekly downloads
FPGA-Based USB-Input Audio Digital to Analogue Converter
the goal of this project is to build a stack for Lonworks Protocol and device working on this protocol
Tools for FPGA development and IP cores. This project provides tools, cores and documentation to develope FPGA applications. The project focuses on VHDL.105 weekly downloads
FreeCores is a project to provide and foster a place for the sharing and development of hardware designs, in the spirit of freedom, starting with all the Free Hardware cores moved from OpenCores.org, and indexed at FreeCores.org.
Frupo stands for Frugal Processor. The idea is to create a small footprint,implementation independent,soft core optimized for easy C programming. The project involves creation of the core itself as well as a toolchain to support it.
This project includes 2 parts: the open FPGA+DSP architecture for the GPS hardware and the GPS software running in embedded system and PC
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GPS to Radio-controlled Clock1 weekly downloads
This project aims at creating an open-source SoC that will support the Google TV platform.
Scanning Probe Microscopy Controller and Data Visualization Software7 weekly downloads
Galaxy Intellectual Property Cores
Project that converts the Gameboy advance into a oscilloscope with a frequency range of 0-50MHZ
This project aims to collect generic arithmetic modules described in VHDL into one library for further reuse.
Genode FX is a composition of hardware and software components that enable the creation of fully fledged graphical user interfaces as system-on-chip solutions using commodity FPGAs such as Xilinx' Spartan3 and Virtex FPGAs.2 weekly downloads
Implementação de um serviço de otimização de funções baseado em Algorítmos Genéticos em um Hardware dedicado e disponível para utilização através de uma interface Web
Este proyecto presenta GraphUIS, una implementación de un periférico de video en un FPGA como un diseño modular caracterizado por no tener memoria dedicada. Se desarrolló como un proyecto académico en la Universidad Industrial de Santander.
An implementation of neural graphs
The H.264 VHDL core is a hardware implementation of the H.264 video compression algorithm. The core accepts up to the highest resolution HDTV video stream as input and outputs the encoded bitstream. Simple, fully synchronous design with low gate count.
This project includes a set of tools and guidelines designed for rapid production of large-scale embedded systems projects. The tools enable quick generation of reusable, reconfigurable hardware, using a user-specified hardware description language.
Platform for advanced open source IP-Core development, i. e. dynamic memory controllers for FPGAs.
This project aims to develop a colour-based vision processing system for use in RoboCup. We are using a CCD camera for input to an FPGA. The system locates coloured objects and outputs detected corners.
This project is to design a high speed vision system used in RoboCup.It involves integrating an FPGA onto the current robotic platform and implement software to do object recognition and provide useful informations to the rest of Robotic system.
The RoboCup Team of Shanghai University (aka. Strive Team) is now devoting itself to the Humanoid League Contest. Many features like machine vision, pace generation, speech cognition, etc. of the humanoid robots is rising here in the following years.
Icarus Verilog is an open source Verilog compiler that supports the IEEE-1364 Verilog HDL including IEEE1364-2005 plus extensions.199 weekly downloads