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- Programming Language: VHDL/Verilog ×
Scicos-HDL is a tool to design digital circuit system; it integrates the hardware circuit, algorithm and Scilab/Scicos environment as a plat for digital circuit design, simulation and Hardware Description Language generation.
Simple RISC microprocessor development project
Verilog Finite State Machine (FSM) Code Generator
Susara is a development architecture for software-defined radio (SDR) applications. It assists developers to focus on the high-level design of radio components, from which efficient platform-specific source code is automatically generated.
Synthesia is an open hardware/software platform intended for creating standalone audio devices such as synthesizers on embedded processors.
HW(VHDL) and SW of logic analyzer and On-Chip-Verification(OCV) for Value Change Dump(VCD) file format that exported to seemd SystemC ,ModelSIM, and many other EDA tools. Very easy and Simple.
This is a collection of tools and a code library to assist engineers who are developing SystemVerilog based verification environments. Components include utility libraries, scoreboard and shutdown manager implementation, register tool, etc.
Make your own virtual FPGA system and profile deeply with CI.
The HDL Complexity Tool parses large complex hardware projects' source code to produce useful complexity results. GOALS: 1)Practical, effective and simple 2) Integrates with existing design flows 3) Used on real projects 4) Based on existing research
The SBus is a family of high-speed packet-based databus standards, suitable for both networking and interdevice communication. They are optimized for high data density transactions. This project creates and documents the standards, schematics, and driver
The goal of this project is to develop an easily modifiable combination of VHDL firmware and LabView drivers for use with laboratory automation control and data acquisition using Terasic's DE2 board and the ISP1362 USB interface chip.
Academic project of USB controller
VHDL description of a FPGA-based FBG interrogation system
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Oscilloscope using a VGA monitor and a cpld
VHDL FSM Generator, like the name says, is an application that will allow you to easily generate a finite state machine in VHDL without any (or very little) VHDL knowledge. The source code was programmed in Delphi 7.
The VHDL Lookup Table Generator generates a table in vhdl from a C++-table. I was too lazy to write a parser. Code is found in the CVS (scroll down for url): http://vhdl-lut-gen.cvs.sourceforge.net/*checkout*/vhdl-lut-gen/vhdl-lut-gen/vhdl-lut-gen.cpp
Application defines templates of VHDL structures, which allows us comfortly generate most used VHDL structures. It can also work with VHDL testbench templates from which can be created VHDL testbenches of existing projects.
Writing Testbenches for FPGA/ASIC design is always a very fastidious and boring task. This project helps any FPGA/ASIC designer by providing a full RTL test environment with C support.
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In this project a simple WAV player will be implemented using an FPGA. The WAV player is able to play music which is digitally stored in a semiconductor memory device. Check out from trunk or use the taged version from download.
Devellopement d'un controlleur d'affichage (VIC) du commodore 64 embarqué dans un FPGA avec controlleur d'animation integré.
Tool-independent Makefile generator for VHDL models.
vcomp is a verilog compiler for x86 linux targets - it was a commercial product which is now in the process of being GPL'd
Compiler-like program that checks Verilog source for common design errors. This tool can help beginning Verilog programmers who aren't aware of common design pitfalls and advanced Verilog programmers who want to double check large projects.
The Verilog-Perl distribution provides Perl preprocessing, parsing and utilities for the Verilog Language. It is also available from CPAN under the Verilog:: namespace.
This project aims to generate video signal using an FPGA development board