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- Programming Language: VHDL/Verilog ×
The OS561 operating system based around FORTH/Java. The OS is to run on a VHDL chip OpenHardware design called the Minon, but could become available for other platforms. The unique point of the design is a revolutionary data compression technology.
This card will capture High Definition Video 1280x720 at 30fps, and soon be capable of 60fps and maybe even 1080p. This is a hardware project so source code, RTL, and board CAD files will be involved. All IC's and parts should be easily available.
A hardware project to interface a microcontroller (currently PIC family) to a LED driver consisting of a CPLD to drive an LED array with 35 LEDs... The source codes (c/vhdl) and schematics are going to be freely available
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Open RVC-CAL to HDL (ORC2HDL) is an Eclipse Plugin which uses the Open RVC-CAL Compiler (ORCC) and the openForge HDL Synthesizer. This plugin gives the ability to generate HDL code from a RVC-CAL model.
OpenWebServo is an Open Source Hardware and Software project. Its main goal is to develop a web-controlled servo system. The project includes web application, firmware and hardware design.
Software to support the JTAG bus (IEEE 1149.1). Primary purpose is for a JTAG programmer/debugger using FPGA's to provide ability to test and program JTAG devices.
Open architecture GPU simulator and implementation
A software package that will combine different embedded computing platforms with home exercise equipment and a Qt client program in order to provide tracking of health and exercise performance.
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Design and implementation of silicon and software for baseband processors conforming to IEEE wireless standards. Initial focus on WiMAX and WiFi.
The main target of this project is to create a Open Source System on Chip generator for FPGA. This generator will use following technologies: Python, Wishbone SoC bus specifications and VHDL.
This is a hardware/software simple USB Digital Storage Oscilloscope project.
Ospu is a soft processor for FPGA.
A methodology to create netlists for printed circuit board layout using a novel PCB specific HDL as the source language.
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Programmable Electronic Controller
Code and documentation for the PSU Mars Society Rover
Palette for computer architecture design
Parallelsimu provides interfaces for parallel simulation of RTL descriptions of complex hardware designs(SoCs, CPUs and etc.) written in Verilog HDL.
ThousandEyes extends visibility across corporate networks as well as the public Internet, helping to solve issues from the branch through MPLS links and SIP trunks to service provider networks. Simulate pre-deployment capacity, monitor detailed performance metrics and see how QoS settings impact call quality.Advertisement
Framework for Adaptive Hardware Concurrent Systems with DPR-FPGAs
Electronic design and programming tools suite like Eagle, MpLab
A simple processor which has an 8-bit data bus and a 13 bit address bus. The memory is 8192 x 8, instructions are 8 or 16 bits wide, and all opcodes are 3 or 4 bits wide.
Ray Tracing micro-processor RTMP. Features: * Programmable pixel shaders. * SIMD 32-bit ALU. * Hardware support for Octree scene traversal. * Ray intersection cache. * Support for mutiple instances of RTMP working concurrently.
A Verilog design for a simple ASIC that executes the Ray Tracing Algorithm.
Este proyecto es una iniciativa para reconstruir la plataforma PUMA MA2000 de la empresa TeQuipment ltd. por medio de la implementación de un sistema empotrado basado en tecnología FPGA.
Collection of VHDL libraries for ASIC/FGPA development