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Context for your AI agents
Crawl websites, sync to vector databases, and power RAG applications. Pre-built integrations for LLM pipelines and AI assistants.
Build data pipelines that feed your AI models and agents without managing infrastructure. Crawl any website, transform content, and push directly to your preferred vector store. Use 10,000+ tools for RAG applications, AI assistants, and real-time knowledge bases. Monitor site changes, trigger workflows on new data, and keep your AIs fed with fresh, structured information. Cloud-native, API-first, and free to start until you need to scale.
cMIPS - an FPGA ready VHDL model for 5-stage pipeline, MIPS32r2 core
This project was moved to https://gitlab.c3sl.ufpr.br/roberto/cmips
The code here is no longer up to date.
The VHDL model mimics the pipeline design described in Patterson & Hennessy's book (Computer Organisation and Design) and is an almost complete implementation of the MIPS32r2 instruction set. The TLB and assorted control registers will be included soon (as of fev 2015). The model was synthesized for an Altera EP4CE30F23.