Search Results for "risc-none-embed-gcc"

A processor that works encrypted, based around the "wally" public RISCV implementation. This implementation of the `KPU' encrypted computing model makes no changes to the standard RISCV processor core other than broadening all paths to 128 bits instead of 32/64. It works instead via additional peripheral units and extra custom RISCV instructions.

A new 64-bit RISC platform, complemented by a set of development tools, standards specifications and synthesizable VHDL implementations.

This project implements a reduced instruction set (RISC) CPU in VHDL. It was designed for the Altera Flex10k20 chip, but the VHDL code should port to any compatable chip. The instruction set is extensive, and the design is easily extendable to 16 bits.

gasVM is a 32-bit, register-based virtual machine that has been designed to support a game that the author has undertaken for the development of a game for a game Competition, "Gary's Adventure of Science!" It is designed so that it may one day be implemented and hardware, and is designed to be a RISC machine. While this VM is designed for a single game, it is hoped that it will be useful for others who are looking for a virtual machine platform to embed within their software.