Search Results for "jd-core"

...As well as an editor, The following utilities are supplied * Formatted Compare * File Copy and reformat Utility * FileWizard this is use to work out the format of a File. It can generally find both Text and binary / packed deicimal fields in a file For Simple Csv you should look at its sister project reCsvEditor. Note: The core Editor code is also used in the "Protocol buffers editor" and "Avro Editor"

A processor that works encrypted, based around the "wally" public RISCV implementation. This implementation of the `KPU' encrypted computing model makes no changes to the standard RISCV processor core other than broadening all paths to 128 bits instead of 32/64. It works instead via additional peripheral units and extra custom RISCV instructions.

This project is based on the sourceforge project tn5250j. The intention of this tn5250jEngine project was to capsulate a slim core modul interpreting the Telnet 5250 stream. This core module provides a 5250-ScreenGrid Interface for any GUI application.

BlowfishVHDL - free fully synthesizable Blowfish encryption algorithm hardware implementation.

lpcusb is a USB core stack for the built-in USB device of LPC214x microcontrollers. It handles the hardware interface and USB enumeration/configuration. Included are usage examples like USB joystick HID, USB virtual COM port and USB mass storage on SD-ca

CPU Informer - CPU recognition program. A very useful tool for CPU detection. It recognizez all types of x86 CPU's including new Intel and AMD Dual Core CPUs. Also CPU Informer can work with most popular LPC SuperIO sensors.

Maiden-core is a Linux kernel robotics API module, extensible in Erc. The Maiden Project also documents and develops the Maiden architecture for mobile robots, a set of (optional) designs and standards for robots using the Maiden-core API.

JSR is a simple J2EE / Struts application with the actual server state : Hard Drives, Ethernet, JVM, Core information, Memory

Pancham is an IP core that implements the MD5 message digest algorithm. It is written in Verilog and comes with a testbench. It will be portable across multiple simulators and will be synthesizable.