3 projects for "testbench" with 2 filters applied:

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  • 1
    VTracer is a Verilog Testbench developer aid. Contains well documented Verilog-Perl co-simulation environment (TCP sockets based), structural Verilog parser, demo Testbenches.
    Downloads: 9 This Week
    Last Update:
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  • 2

    ASDM-NoC

    Asynchronous Spatial Division Multiplexing Router for On-Chip Networks

    ...Features: * 5-port router for mesh network (0 south, 1 west, 2 north, 3 east, 4 local) * The dimension order routing (XY routing) * Available flow control methods: wormhole, SDM, VC * Reconfigurable number of virtual circuits, buffer size, data width * Fully synthesizable router implementation * SystemC testbench provided Languages: * Routers are written in synthesizable SystemVerilog * Test benches are provided by SystemC Software requirements: * The open source Nangate 45nm cell library * Synopsys Design Compiler (Synthesis) * Cadence IUS -- NC Simulator (for SystemC/Verilog co-simulation)
    Downloads: 0 This Week
    Last Update:
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  • 3
    Pancham is an IP core that implements the MD5 message digest algorithm. It is written in Verilog and comes with a testbench. It will be portable across multiple simulators and will be synthesizable.
    Downloads: 0 This Week
    Last Update:
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