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This is a standalone preprocessor for the Verilog HDL language.
It is modified from the Verilog-PreProcessor of Verilog Perl tool 3.314.
Most of the code is written by the team led by Wilson Snyder.
What I have done in this project:
* Provide a standalone command line interface (without Perl).
* Replace the parts implemented in Perl to C++.
* Encapsulate the package in a separated namespace for better independence.
What I may do in the future:
* Replace the C language features to...
We are currently developing our embedded TCP/IP modules, industrial ethernet systems and wireless platform for system control and data acquisition. Our main development environment is Linux and GNU tools like GCC (ASM, C, C++) and Python.