Search Results for "processor set"

Argus Monitor is a powerful fan-control and system-monitoring tool that gives you complete control over cooling behavior across your entire PC. It allows you to manage CPU, GPU, motherboard, and AIO fans using fixed values or advanced temperature-based control curves sourced from any sensor in your system. With multi-controller support, fan profiles, hysteresis, and temperature averaging, Argus Monitor offers smooth, precise fan adjustments with minimal noise fluctuation. The software also...

This project was moved to https://gitlab.c3sl.ufpr.br/roberto/cmips The code here is no longer up to date. The VHDL model mimics the pipeline design described in Patterson & Hennessy's book (Computer Organisation and Design) and is an almost complete implementation of the MIPS32r2 instruction set. The TLB and assorted control registers will be included soon (as of fev 2015). The model was synthesized for an Altera EP4CE30F23. The model uses up 15% of combinational blocks and 5%...

OpenSOC86 is an open implementation of the x86 architecture in Verilog. The current version only implements the 16-bit part (real mode). The processor is a pipelined architecture clocked at 100 MHz in a Cyclone II speed grade -6. Therefore it can be seen as similar to a 486 in real mode. Several peripherals are also implemented in a somewhat minimalistic way, but enough to be able to boot an IBM PCXT compatible bios and MSDOS 6.22. The current implementation is only proven to boot the...

The Python Hardware Processsor is a implementation of a Hardware CPU in Myhdl. The CPU can directly execute something very similar to python bytecode (but only a very restricted instruction set). The Programm code for the CPU can be written directly in python (very restricted parts of python). This code is then converted by a small python programm to this restricted python bytecode. Since the hardware description is also in python, the slightly modified bytecode an then automatically loaded...

The project creates a standard for Java implementations of ARM applications. It uses an asynchronous event model with threading that is standard for any board the runs Java on an ARM processor. The set of interfaces, abstract classes, events and enums create a standard that help enforce the write once, run anywhere credo. This will make code more portable and readable. Main Area: https://sourceforge.net/p/armature/discussion/